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| author | Will Deacon <will.deacon@arm.com> | 2011-11-22 17:30:28 (GMT) |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2011-12-08 10:30:38 (GMT) |
| commit | d675d0bc47f28c5414fbbe17fcc801f69c45b960 (patch) | |
| tree | 78d7b2c43650d6af96caac9e631409cf15c8f25a /arch/arm/kernel/head.S | |
| parent | 8d2cd3a38fd663bd341507f5ac29002ffd81d986 (diff) | |
| download | linux-fsl-qoriq-d675d0bc47f28c5414fbbe17fcc801f69c45b960.tar.xz | |
ARM: LPAE: add ISBs around MMU enabling code
Before we enable the MMU, we must ensure that the TTBR registers contain
sane values. After the MMU has been enabled, we jump to the *virtual*
address of the following function, so we also need to ensure that the
SCTLR write has taken effect.
This patch adds ISB instructions around the SCTLR write to ensure the
visibility of the above.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm/kernel/head.S')
| -rw-r--r-- | arch/arm/kernel/head.S | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 64e9943..54eb94a 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -401,8 +401,10 @@ ENDPROC(__enable_mmu) .pushsection .idmap.text, "ax" ENTRY(__turn_mmu_on) mov r0, r0 + instr_sync mcr p15, 0, r0, c1, c0, 0 @ write control reg mrc p15, 0, r3, c0, c0, 0 @ read id reg + instr_sync mov r3, r3 mov r3, r13 mov pc, r3 |