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authorLudovic Desroches <ludovic.desroches@atmel.com>2012-06-21 12:47:27 (GMT)
committerNicolas Ferre <nicolas.ferre@atmel.com>2012-07-02 12:26:59 (GMT)
commit8fe82a5550a8e97b3f59c74f994b88ed6b3544a3 (patch)
tree0b46bdd7cfe2bb0691bf8c3243f803b478fe4379 /arch/arm/mach-at91/include
parent3e135466745a62b1814edef74c7b4a25e6bda707 (diff)
downloadlinux-fsl-qoriq-8fe82a5550a8e97b3f59c74f994b88ed6b3544a3.tar.xz
ARM: at91: sparse irq support
Enable sparse irq support for multisoc image. It involves to add the NR_IRQS_LEGACY offset to static SoC irq number definitions since NR_IRQS_LEGACY irq descs are allocated before AIC requests irq descs allocation. Move NR_AIC_IRQS macro to a more appropiate place with the purpose to remove mach/irqs.h later. Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat (limited to 'arch/arm/mach-at91/include')
-rw-r--r--arch/arm/mach-at91/include/mach/at91_aic.h3
-rw-r--r--arch/arm/mach-at91/include/mach/irqs.h12
2 files changed, 3 insertions, 12 deletions
diff --git a/arch/arm/mach-at91/include/mach/at91_aic.h b/arch/arm/mach-at91/include/mach/at91_aic.h
index 7867378..fd42a85 100644
--- a/arch/arm/mach-at91/include/mach/at91_aic.h
+++ b/arch/arm/mach-at91/include/mach/at91_aic.h
@@ -28,6 +28,9 @@ extern void __iomem *at91_aic_base;
.extern at91_aic_base
#endif
+/* Number of irq lines managed by AIC */
+#define NR_AIC_IRQS 32
+
#define AT91_AIC_IRQ_MIN_PRIORITY 0
#define AT91_AIC_IRQ_MAX_PRIORITY 7
diff --git a/arch/arm/mach-at91/include/mach/irqs.h b/arch/arm/mach-at91/include/mach/irqs.h
index 2d510ee..cab60d5 100644
--- a/arch/arm/mach-at91/include/mach/irqs.h
+++ b/arch/arm/mach-at91/include/mach/irqs.h
@@ -22,18 +22,6 @@
#define __ASM_ARCH_IRQS_H
#include <linux/io.h>
-#include <mach/at91_aic.h>
-
-#define NR_AIC_IRQS 32
-
-
-/*
- * IRQ interrupt symbols are the AT91xxx_ID_* symbols
- * for IRQs handled directly through the AIC, or else the AT91_PIN_*
- * symbols in gpio.h for ones handled indirectly as GPIOs.
- * We make provision for 5 banks of GPIO.
- */
-#define NR_IRQS (NR_AIC_IRQS + (5 * 32))
/* FIQ is AIC source 0. */
#define FIQ_START AT91_ID_FIQ