summaryrefslogtreecommitdiff
path: root/arch/arm/mach-kirkwood/pcie.c
diff options
context:
space:
mode:
authorAndrew Lunn <andrew@lunn.ch>2012-03-08 20:45:59 (GMT)
committerMike Turquette <mturquette@linaro.org>2012-05-08 23:34:02 (GMT)
commit27e53cfbce493bb062212263aa24bbbc5a1077f4 (patch)
treea017e6bcfa6f5ebeb152475c8b3b19fefd73b902 /arch/arm/mach-kirkwood/pcie.c
parentc510182b1c68e2f2bf61e69f6c65bcf61a188809 (diff)
downloadlinux-fsl-qoriq-27e53cfbce493bb062212263aa24bbbc5a1077f4.tar.xz
ARM: Orion: PCIE: Add support for clk
Prepare and enable the clocks when the board indicates the pcie buses will be used. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Jamie Lentin <jm@lentin.co.uk> Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'arch/arm/mach-kirkwood/pcie.c')
-rw-r--r--arch/arm/mach-kirkwood/pcie.c20
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index f56a011..881933a 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -11,6 +11,7 @@
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/slab.h>
+#include <linux/clk.h>
#include <video/vga.h>
#include <asm/irq.h>
#include <asm/mach/pci.h>
@@ -19,6 +20,23 @@
#include <plat/addr-map.h>
#include "common.h"
+static void kirkwood_enable_pcie_clk(const char *port)
+{
+ struct clk *clk;
+
+ clk = clk_get_sys("pcie", port);
+ if (IS_ERR(clk)) {
+ printk(KERN_ERR "PCIE clock %s missing\n", port);
+ return;
+ }
+ clk_prepare_enable(clk);
+ clk_put(clk);
+}
+
+/* This function is called very early in the boot when probing the
+ hardware to determine what we actually are, and what rate tclk is
+ ticking at. Hence calling kirkwood_enable_pcie_clk() is not
+ possible since the clk tree has not been created yet. */
void kirkwood_enable_pcie(void)
{
u32 curr = readl(CLOCK_GATING_CTRL);
@@ -183,10 +201,12 @@ static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
switch (index) {
case 0:
kirkwood_clk_ctrl |= CGC_PEX0;
+ kirkwood_enable_pcie_clk("0");
pcie0_ioresources_init(pp);
break;
case 1:
kirkwood_clk_ctrl |= CGC_PEX1;
+ kirkwood_enable_pcie_clk("1");
pcie1_ioresources_init(pp);
break;
default: