diff options
author | David Brown <davidb@codeaurora.org> | 2011-01-04 19:02:59 (GMT) |
---|---|---|
committer | David Brown <davidb@codeaurora.org> | 2011-01-21 23:27:50 (GMT) |
commit | 8bb06444804c58dffcb5d048381c6378d2b007f7 (patch) | |
tree | 2397d12f923ffce2cbb78df59d576506c63d814a /arch/arm/mach-msm/include | |
parent | 8c27e6f305242ffab0c88eed5dea8394b8ce86d0 (diff) | |
download | linux-fsl-qoriq-8bb06444804c58dffcb5d048381c6378d2b007f7.tar.xz |
msm: Generalize QGIC registers
The QGIC registers are mapped to the same virtual addresses across
targets, only the physical address changes. Move the BASE address out
of target-specific files, and add a SOC name to the base addresses.
Signed-off-by: David Brown <davidb@codeaurora.org>
Diffstat (limited to 'arch/arm/mach-msm/include')
-rw-r--r-- | arch/arm/mach-msm/include/mach/msm_iomap-8x60.h | 10 | ||||
-rw-r--r-- | arch/arm/mach-msm/include/mach/msm_iomap.h | 2 |
2 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h index d5482d6..5bd18db 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h @@ -35,13 +35,11 @@ * */ -#define MSM_QGIC_DIST_BASE IOMEM(0xF0000000) -#define MSM_QGIC_DIST_PHYS 0x02080000 -#define MSM_QGIC_DIST_SIZE SZ_4K +#define MSM8X60_QGIC_DIST_PHYS 0x02080000 +#define MSM8X60_QGIC_DIST_SIZE SZ_4K -#define MSM_QGIC_CPU_BASE IOMEM(0xF0001000) -#define MSM_QGIC_CPU_PHYS 0x02081000 -#define MSM_QGIC_CPU_SIZE SZ_4K +#define MSM8X60_QGIC_CPU_PHYS 0x02081000 +#define MSM8X60_QGIC_CPU_SIZE SZ_4K #define MSM_ACC_BASE IOMEM(0xF0002000) #define MSM_ACC_PHYS 0x02001000 diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h index 0243bd0..bb42de3 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap.h @@ -55,6 +55,8 @@ /* Virtual addressses shared across all MSM targets. */ #define MSM_CSR_BASE IOMEM(0xE0001000) +#define MSM_QGIC_DIST_BASE IOMEM(0xF0000000) +#define MSM_QGIC_CPU_BASE IOMEM(0xF0001000) #define MSM_TMR_BASE IOMEM(0xF0200000) #define MSM_TMR0_BASE IOMEM(0xF0201000) |