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author | Linus Torvalds <torvalds@linux-foundation.org> | 2011-11-06 01:18:05 (GMT) |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2011-11-06 01:18:05 (GMT) |
commit | 7abec10c623d9e0416dab6919a0ea22e6283516b (patch) | |
tree | 83aa79c369e99c4fc60eea91ebd399b7689b312e /arch/arm/mach-s3c64xx/clock.c | |
parent | 0de9adf284ec20454ecf37ffd98e7e98ba7292d6 (diff) | |
parent | cfaf8fc5b59527281e9ddc2e0e04e1127936e17f (diff) | |
download | linux-fsl-qoriq-7abec10c623d9e0416dab6919a0ea22e6283516b.tar.xz |
Merge branch 'next/cleanup3' of git://git.linaro.org/people/arnd/arm-soc
* 'next/cleanup3' of git://git.linaro.org/people/arnd/arm-soc: (79 commits)
ARM: SAMSUNG: Move fimc plat. device from board files to plat-samsung
ARM: SAMSUNG: Cleanup resources by using macro
ARM: SAMSUNG: Cleanup plat-samsung/devs.c and devs.h
ARM: S5P: To merge devs.c files to one devs.c
ARM: S3C64XX: To merge devs.c files to one devs.c
ARM: S3C24XX: To merge s3c24xx devs.c files to one devs.c
ARM: S5P64X0: Add Power Management support
ARM: S5P: Make the sleep code common for S5P series SoCs
ARM: S5P: Make the common S5P PM code conditionally compile
ARM: SAMSUNG: Move S5P header files to plat-samsung
ARM: SAMSUNG: Move S3C24XX header files to plat-samsung
ARM: SAMSUNG: Moving each SoC support header files
ARM: SAMSUNG: Consolidate plat/pll.h
ARM: SAMSUNG: Consolidate plat/pwm-clock.h
ARM: SAMSUNG: Cleanup mach/clkdev.h
ARM: SAMSUNG: remove sdhci default configuration setup platform helper
ARM: EXYNOS4: Add FIMC device on SMDKV310 board
ARM: EXYNOS4: Add header file protection macros
ARM: EXYNOS4: Add usb ehci device to the SMDKV310
ARM: S3C2443: Add hsspi-clock from pclk and rename S3C2443 hsspi sclk
...
Fix up conflicts in
- arch/arm/mach-exynos4/{Kconfig,clock.c}
ARM_CPU_SUSPEND, various random device tables (gah!)
- drivers/gpio/Makefile
sa1100 gpio added, samsung gpio drivers merged
Diffstat (limited to 'arch/arm/mach-s3c64xx/clock.c')
-rw-r--r-- | arch/arm/mach-s3c64xx/clock.c | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c index 8cf39e3..39c238d 100644 --- a/arch/arm/mach-s3c64xx/clock.c +++ b/arch/arm/mach-s3c64xx/clock.c @@ -25,13 +25,13 @@ #include <mach/regs-sys.h> #include <mach/regs-clock.h> -#include <mach/pll.h> #include <plat/cpu.h> #include <plat/devs.h> #include <plat/cpu-freq.h> #include <plat/clock.h> #include <plat/clock-clksrc.h> +#include <plat/pll.h> /* fin_apll, fin_mpll and fin_epll are all the same clock, which we call * ext_xtal_mux for want of an actual name from the manual. @@ -735,7 +735,8 @@ void __init_or_cpufreq s3c6400_setup_clocks(void) /* For now assume the mux always selects the crystal */ clk_ext_xtal_mux.parent = xtal_clk; - epll = s3c6400_get_epll(xtal); + epll = s3c_get_pll6553x(xtal, __raw_readl(S3C_EPLL_CON0), + __raw_readl(S3C_EPLL_CON1)); mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON)); apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON)); @@ -744,7 +745,13 @@ void __init_or_cpufreq s3c6400_setup_clocks(void) printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n", apll, mpll, epll); - hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2); + if(__raw_readl(S3C64XX_OTHERS) & S3C64XX_OTHERS_SYNCMUXSEL) + /* Synchronous mode */ + hclk2 = apll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2); + else + /* Asynchronous mode */ + hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2); + hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK); pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK); |