diff options
author | Stephen Warren <swarren@nvidia.com> | 2012-02-07 01:09:15 (GMT) |
---|---|---|
committer | Olof Johansson <olof@lixom.net> | 2012-02-26 22:16:28 (GMT) |
commit | e186ad74c0941f5caeda28bde76dab903b342c1c (patch) | |
tree | e92b60b51487b53399d89552a2ec514a9d5b021c /arch/arm/mach-tegra | |
parent | 64092d8f34774429a2519622e5cf0ca63b1ba517 (diff) | |
download | linux-fsl-qoriq-e186ad74c0941f5caeda28bde76dab903b342c1c.tar.xz |
ARM: tegra: Demote EMC clock inconsistency BUG to WARN
When this inconsistency occurs, the system will typically operate without
issue, it's just that EMC scaling won't optimally. Convert the BUG_ON to
a WARN_ONCE in order to allow the kernel to boot, but still complain.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/mach-tegra')
-rw-r--r-- | arch/arm/mach-tegra/tegra2_clocks.c | 30 |
1 files changed, 25 insertions, 5 deletions
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c index ff9e6b6..1976e93 100644 --- a/arch/arm/mach-tegra/tegra2_clocks.c +++ b/arch/arm/mach-tegra/tegra2_clocks.c @@ -1143,15 +1143,35 @@ static void tegra2_emc_clk_init(struct clk *c) static long tegra2_emc_clk_round_rate(struct clk *c, unsigned long rate) { - long new_rate = rate; + long emc_rate; + long clk_rate; - new_rate = tegra_emc_round_rate(new_rate); - if (new_rate < 0) + /* + * The slowest entry in the EMC clock table that is at least as + * fast as rate. + */ + emc_rate = tegra_emc_round_rate(rate); + if (emc_rate < 0) return c->max_rate; - BUG_ON(new_rate != tegra2_periph_clk_round_rate(c, new_rate)); + /* + * The fastest rate the PLL will generate that is at most the + * requested rate. + */ + clk_rate = tegra2_periph_clk_round_rate(c, emc_rate); + + /* + * If this fails, and emc_rate > clk_rate, it's because the maximum + * rate in the EMC tables is larger than the maximum rate of the EMC + * clock. The EMC clock's max rate is the rate it was running when the + * kernel booted. Such a mismatch is probably due to using the wrong + * BCT, i.e. using a Tegra20 BCT with an EMC table written for Tegra25. + */ + WARN_ONCE(emc_rate != clk_rate, + "emc_rate %ld != clk_rate %ld", + emc_rate, clk_rate); - return new_rate; + return emc_rate; } static int tegra2_emc_clk_set_rate(struct clk *c, unsigned long rate) |