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| author | Linus Walleij <linus.walleij@stericsson.com> | 2009-08-15 14:12:05 (GMT) |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-09-18 21:09:02 (GMT) |
| commit | ee2b805c8eb6459cf541ef141ff70dae17af59ca (patch) | |
| tree | ca1e0f1988e71f2285ca336d88c5da2c5efa8c71 /arch/arm/mach-u300 | |
| parent | a2ca00ea9398265a26eabb358bba83c8b75c463d (diff) | |
| download | linux-fsl-qoriq-ee2b805c8eb6459cf541ef141ff70dae17af59ca.tar.xz | |
ARM: 5678/1: SSP/SPI PL022 polarity terminology fix
The definition of the SPI clock phase for the Motorola mode of
the PL022 driver was incorrect: the spec had been interpreted as
data being recieved on rising or falling edge of the clocks while
the correct interpretation is that data can be recieved on the
first or second edge transition, falling or rising depending on
the polarity setting.
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-u300')
| -rw-r--r-- | arch/arm/mach-u300/spi.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-u300/spi.c b/arch/arm/mach-u300/spi.c index 307d007..f0e887b 100644 --- a/arch/arm/mach-u300/spi.c +++ b/arch/arm/mach-u300/spi.c @@ -48,7 +48,7 @@ struct pl022_config_chip dummy_chip_info = { .data_size = SSP_DATA_BITS_8, /* used to be 12 in some default */ .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM, .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC, - .clk_phase = SSP_CLK_FALLING_EDGE, + .clk_phase = SSP_CLK_SECOND_EDGE, .clk_pol = SSP_CLK_POL_IDLE_LOW, .ctrl_len = SSP_BITS_12, .wait_state = SSP_MWIRE_WAIT_ZERO, |