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authorLinus Torvalds <torvalds@linux-foundation.org>2012-07-23 23:22:12 (GMT)
committerLinus Torvalds <torvalds@linux-foundation.org>2012-07-23 23:22:12 (GMT)
commitfde75430278130505cac21997cd9f90b7bb2670a (patch)
tree909f659117f5fa8bf1b9b46809f4dc655aee0d34 /arch/arm/plat-omap/include/plat/omap_hwmod.h
parent1a4120bc101bdc25ec7258937b5071bf34b19cc5 (diff)
parentdb3c47a3af96e8109b1bb114c32f0854259d5970 (diff)
downloadlinux-fsl-qoriq-fde75430278130505cac21997cd9f90b7bb2670a.tar.xz
Merge tag 'cleanup2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull arm-soc cleanups, part 2, from Arnd Bergmann: "These omap cleanups have dependencies on earlier omap branches that in turn depend on other cleanups, so they could not go into the same branch." * tag 'cleanup2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: ARM: OMAP: sdrc: Fix the build break for OMAP4 only builds ARM: OMAP2+: dmtimer: cleanup fclk usage ARM: OMAP2+: Fix mismerge for omap_hwmod_get_main_clk() API ARM: OMAP2+: Remove unnecessary ifdef around __omap2_set_globals ARM: OMAP2+: am33xx: Change cpu_is_am33xx to soc_is_am33xx ARM: OMAP2+: am33xx: Make am33xx as a separate class ARM: OMAP2+: Move omap3 dpll ops to dpll3xxx.c ARM: OMAP2+: All OMAP2PLUS uses omap-device.o target so add one entry ARM: OMAP: dmtimer: use devm_ API and do some cleanup in probe() ARM: OMAP2+: hwmod code: add support to set dmadisable in hwmod framework ARM: OMAP2+: PRM/CM: Move the stubbed prm and cm functions to prcm.c file and make them __weak ARM: OMAP2+: hwmod: add omap_hwmod_get_main_clk() API ARM: OMAP3+: dpll: optimize noncore dpll locking logic ARM: OMAP3: control: add definition for CONTROL_CAMERA_PHY_CTRL ARM: OMAP2+: powerdomain code: Fix Wake-up power domain power status ARM: OMAP4: clockdomain/CM code: Update supported transition modes ARM: OMAP3/4: omap_hwmod: Add rstst_offs field to struct omap_hwmod_omap4_prcm ARM: OMAP2+: hwmod: Add new sysc_type3 into omap_hwmod required for am33xx
Diffstat (limited to 'arch/arm/plat-omap/include/plat/omap_hwmod.h')
-rw-r--r--arch/arm/plat-omap/include/plat/omap_hwmod.h19
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index a8ecc53..6132972 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -41,6 +41,7 @@ struct omap_device;
extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type1;
extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2;
+extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type3;
/*
* OCP SYSCONFIG bit shifts/masks TYPE1. These are for IPs compliant
@@ -69,6 +70,17 @@ extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2;
#define SYSC_TYPE2_SIDLEMODE_MASK (0x3 << SYSC_TYPE2_SIDLEMODE_SHIFT)
#define SYSC_TYPE2_MIDLEMODE_SHIFT 4
#define SYSC_TYPE2_MIDLEMODE_MASK (0x3 << SYSC_TYPE2_MIDLEMODE_SHIFT)
+#define SYSC_TYPE2_DMADISABLE_SHIFT 16
+#define SYSC_TYPE2_DMADISABLE_MASK (0x1 << SYSC_TYPE2_DMADISABLE_SHIFT)
+
+/*
+ * OCP SYSCONFIG bit shifts/masks TYPE3.
+ * This is applicable for some IPs present in AM33XX
+ */
+#define SYSC_TYPE3_SIDLEMODE_SHIFT 0
+#define SYSC_TYPE3_SIDLEMODE_MASK (0x3 << SYSC_TYPE3_SIDLEMODE_SHIFT)
+#define SYSC_TYPE3_MIDLEMODE_SHIFT 2
+#define SYSC_TYPE3_MIDLEMODE_MASK (0x3 << SYSC_TYPE3_MIDLEMODE_SHIFT)
/* OCP SYSSTATUS bit shifts/masks */
#define SYSS_RESETDONE_SHIFT 0
@@ -283,6 +295,7 @@ struct omap_hwmod_ocp_if {
#define SYSS_HAS_RESET_STATUS (1 << 7)
#define SYSC_NO_CACHE (1 << 8) /* XXX SW flag, belongs elsewhere */
#define SYSC_HAS_RESET_STATUS (1 << 9)
+#define SYSC_HAS_DMADISABLE (1 << 10)
/* omap_hwmod_sysconfig.clockact flags */
#define CLOCKACT_TEST_BOTH 0x0
@@ -298,6 +311,7 @@ struct omap_hwmod_ocp_if {
* @enwkup_shift: Offset of the enawakeup bit
* @srst_shift: Offset of the softreset bit
* @autoidle_shift: Offset of the autoidle bit
+ * @dmadisable_shift: Offset of the dmadisable bit
*/
struct omap_hwmod_sysc_fields {
u8 midle_shift;
@@ -306,6 +320,7 @@ struct omap_hwmod_sysc_fields {
u8 enwkup_shift;
u8 srst_shift;
u8 autoidle_shift;
+ u8 dmadisable_shift;
};
/**
@@ -374,11 +389,13 @@ struct omap_hwmod_omap2_prcm {
* struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data
* @clkctrl_reg: PRCM address of the clock control register
* @rstctrl_reg: address of the XXX_RSTCTRL register located in the PRM
+ * @rstst_reg: (AM33XX only) address of the XXX_RSTST register in the PRM
* @submodule_wkdep_bit: bit shift of the WKDEP range
*/
struct omap_hwmod_omap4_prcm {
u16 clkctrl_offs;
u16 rstctrl_offs;
+ u16 rstst_offs;
u16 context_offs;
u8 submodule_wkdep_bit;
u8 modulemode;
@@ -631,6 +648,8 @@ int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx);
extern void __init omap_hwmod_init(void);
+const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh);
+
/*
* Chip variant-specific hwmod init routines - XXX should be converted
* to use initcalls once the initial boot ordering is straightened out