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author | Paul Walmsley <paul@pwsan.com> | 2009-06-20 01:08:26 (GMT) |
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committer | paul <paul@twilight.(none)> | 2009-06-20 01:09:31 (GMT) |
commit | c9812d042a21eb492a36cfabf9f41107f5ecee3d (patch) | |
tree | f9443de1d4534b0b56bd1b0ff56bfc6d78eb698d /arch/arm/plat-omap/sram.c | |
parent | 2f135eaf182761bb9a5cbd5138a447b0ad2a1fef (diff) | |
download | linux-fsl-qoriq-c9812d042a21eb492a36cfabf9f41107f5ecee3d.tar.xz |
OMAP3 clock: add a short delay when lowering CORE clk rate
When changing the SDRAM clock from 166MHz to 83MHz via the CORE DPLL M2
divider, add a short delay before returning to SDRAM to allow the SDRC
time to stabilize. Without this delay, the system is prone to random
panics upon re-entering SDRAM.
This time delay varies based on MPU frequency. At 500MHz MPU frequency at
room temperature, 64 loops seems to work okay; so add another 32 loops for
environmental and process variation.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/plat-omap/sram.c')
-rw-r--r-- | arch/arm/plat-omap/sram.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index a5b9bcd..79c0f02 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -371,15 +371,17 @@ static inline int omap243x_sram_init(void) static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, u32 sdrc_actim_ctrlb, - u32 m2, u32 unlock_dll); + u32 m2, u32 unlock_dll, + u32 f); u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, - u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll) + u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll, + u32 f) { BUG_ON(!_omap3_sram_configure_core_dpll); return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl, sdrc_actim_ctrla, sdrc_actim_ctrlb, m2, - unlock_dll); + unlock_dll, f); } /* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */ |