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author | Al Viro <viro@zeniv.linux.org.uk> | 2012-05-19 05:13:01 (GMT) |
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committer | Al Viro <viro@zeniv.linux.org.uk> | 2012-10-01 13:58:14 (GMT) |
commit | e3b880c6ee55e8858a75e3dcf6c3dda04d5e3605 (patch) | |
tree | 6d8ab01a85cd9c36b7480f0725447863f4412903 /arch/arm/plat-s3c24xx/clock-dclk.c | |
parent | 00df111e7eb505558c54f23861e9341e56dd5fb0 (diff) | |
download | linux-fsl-qoriq-e3b880c6ee55e8858a75e3dcf6c3dda04d5e3605.tar.xz |
parisc: don't bother looping in do_signal()
entry.S code had been looping until no pending signals are left
since 2005 anyway; no need to bother with that in do_signal()
itself. If the failure to set a sigframe up raises SIGSEGV,
we'll just pick it up the next time around the loop(s) in entry.S
anyway.
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Diffstat (limited to 'arch/arm/plat-s3c24xx/clock-dclk.c')
0 files changed, 0 insertions, 0 deletions