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author | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-08-10 22:17:52 (GMT) |
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committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-08-10 22:17:52 (GMT) |
commit | 0b019a41553a919965bb02d07d54e3e6c57a796d (patch) | |
tree | 6e329b4159b440d2aac5200a5c07103fe261c096 /arch/arm/plat-s5p/include/plat/pll.h | |
parent | 5f6878b0d22f9b93f9698f88c335007e2a3c3bbc (diff) | |
parent | 054d5c9238f3c577ad51195c3ee7803613f322cc (diff) | |
download | linux-fsl-qoriq-0b019a41553a919965bb02d07d54e3e6c57a796d.tar.xz |
Merge branches 'master' and 'devel' into for-linus
Conflicts:
arch/arm/Kconfig
arch/arm/mm/Kconfig
Diffstat (limited to 'arch/arm/plat-s5p/include/plat/pll.h')
-rw-r--r-- | arch/arm/plat-s5p/include/plat/pll.h | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/arch/arm/plat-s5p/include/plat/pll.h b/arch/arm/plat-s5p/include/plat/pll.h index 7db3227..4e8fe08 100644 --- a/arch/arm/plat-s5p/include/plat/pll.h +++ b/arch/arm/plat-s5p/include/plat/pll.h @@ -46,6 +46,47 @@ static inline unsigned long s5p_get_pll45xx(unsigned long baseclk, u32 pll_con, return (unsigned long)fvco; } +#define PLL46XX_KDIV_MASK (0xFFFF) +#define PLL46XX_MDIV_MASK (0x1FF) +#define PLL46XX_PDIV_MASK (0x3F) +#define PLL46XX_SDIV_MASK (0x7) +#define PLL46XX_MDIV_SHIFT (16) +#define PLL46XX_PDIV_SHIFT (8) +#define PLL46XX_SDIV_SHIFT (0) + +enum pll46xx_type_t { + pll_4600, + pll_4650, +}; + +static inline unsigned long s5p_get_pll46xx(unsigned long baseclk, + u32 pll_con0, u32 pll_con1, + enum pll46xx_type_t pll_type) +{ + unsigned long result; + u32 mdiv, pdiv, sdiv, kdiv; + u64 tmp; + + mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK; + pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK; + sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK; + kdiv = pll_con1 & PLL46XX_KDIV_MASK; + + tmp = baseclk; + + if (pll_type == pll_4600) { + tmp *= (mdiv << 16) + kdiv; + do_div(tmp, (pdiv << sdiv)); + result = tmp >> 16; + } else { + tmp *= (mdiv << 10) + kdiv; + do_div(tmp, (pdiv << sdiv)); + result = tmp >> 10; + } + + return result; +} + #define PLL90XX_MDIV_MASK (0xFF) #define PLL90XX_PDIV_MASK (0x3F) #define PLL90XX_SDIV_MASK (0x7) |