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| author | Chenhui Zhao <chenhui.zhao@freescale.com> | 2015-01-27 09:57:34 (GMT) |
|---|---|---|
| committer | Zhengxiong Jin <Jason.Jin@freescale.com> | 2015-02-05 08:30:31 (GMT) |
| commit | 6e5e07bbbe2808dfa5a176988e4e0a8f9cec944b (patch) | |
| tree | 0072023c09778c215b576cd428d75cd8a37c4e38 /arch/arm | |
| parent | ed45606fb6f0737605ee84aee8495bdc76753cdc (diff) | |
| download | linux-fsl-qoriq-6e5e07bbbe2808dfa5a176988e4e0a8f9cec944b.tar.xz | |
arm: ls1021a: no need to reset the registers after core reset
These registers has been reset in the bootloader after power-up.
No need to reset them in kernel.
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Change-Id: I300f1763bafce3291c371b05d7bce3c363dc760b
Reviewed-on: http://git.am.freescale.net:8181/29620
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhuoyu Zhang <Zhuoyu.Zhang@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/mach-imx/platsmp.c | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c index 140c98c..72f8e5f 100644 --- a/arch/arm/mach-imx/platsmp.c +++ b/arch/arm/mach-imx/platsmp.c @@ -246,14 +246,6 @@ static int ls1021a_reset_secondary(unsigned int cpu) SCFG_CORE0_SFT_RST + STRIDE_4B * cpu); mdelay(15); - /* LS1021a errata. after reset, core state machine registers - * need to force release manually. - */ - iowrite32be(0x00000080, dcsr_rcpm2_base + DCSR_RCPM2_DEBUG1); - iowrite32be(0x00000080, dcsr_rcpm2_base + DCSR_RCPM2_DEBUG2); - iowrite32be(0, dcsr_rcpm2_base + DCSR_RCPM2_DEBUG1); - iowrite32be(0, dcsr_rcpm2_base + DCSR_RCPM2_DEBUG2); - /* Release secondary core */ iowrite32be(1 << cpu, dcfg_base + DCFG_CCSR_BRR); |