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author | Ingo Molnar <mingo@elte.hu> | 2008-06-16 09:19:53 (GMT) |
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committer | Ingo Molnar <mingo@elte.hu> | 2008-06-16 09:19:53 (GMT) |
commit | 064a32d82c20cdcb0119a8b316eb520608d8c647 (patch) | |
tree | c67d534bd4458b1482c11f11c724fe93beca4f80 /arch/blackfin/lib/ins.S | |
parent | 0327318445d55808991a63137cfb698a90ab6adf (diff) | |
parent | 066519068ad2fbe98c7f45552b1f592903a9c8c8 (diff) | |
download | linux-fsl-qoriq-064a32d82c20cdcb0119a8b316eb520608d8c647.tar.xz |
Merge branch 'linus' into x86/memtest
Diffstat (limited to 'arch/blackfin/lib/ins.S')
-rw-r--r-- | arch/blackfin/lib/ins.S | 21 |
1 files changed, 18 insertions, 3 deletions
diff --git a/arch/blackfin/lib/ins.S b/arch/blackfin/lib/ins.S index df7b883..eba2343 100644 --- a/arch/blackfin/lib/ins.S +++ b/arch/blackfin/lib/ins.S @@ -7,7 +7,7 @@ * Description: Implementation of ins{bwl} for BlackFin processors using zero overhead loops. * * Modified: - * Copyright 2004-2006 Analog Devices Inc. + * Copyright 2004-2008 Analog Devices Inc. * Copyright (C) 2005 Bas Vermeulen, BuyWays BV <bas@buyways.nl> * * Bugs: Enter bugs at http://blackfin.uclinux.org/ @@ -63,6 +63,23 @@ ENTRY(_insw) RTS; ENDPROC(_insw) +ENTRY(_insw_8) + P0 = R0; /* P0 = port */ + cli R3; + P1 = R1; /* P1 = address */ + P2 = R2; /* P2 = count */ + SSYNC; + LSETUP( .Lword8_loop_s, .Lword8_loop_e) LC0 = P2; +.Lword8_loop_s: R0 = W[P0]; + B[P1++] = R0; + R0 = R0 >> 8; + B[P1++] = R0; + NOP; +.Lword8_loop_e: NOP; + sti R3; + RTS; +ENDPROC(_insw_8) + ENTRY(_insb) P0 = R0; /* P0 = port */ cli R3; @@ -78,8 +95,6 @@ ENTRY(_insb) RTS; ENDPROC(_insb) - - ENTRY(_insl_16) P0 = R0; /* P0 = port */ cli R3; |