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| author | Soren Brinkmann <soren.brinkmann@xilinx.com> | 2012-12-19 18:18:37 (GMT) |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2013-01-28 12:27:21 (GMT) |
| commit | af7f032dba8ccf7ee430a48656d25565672a6074 (patch) | |
| tree | 00594280fae0fed8a1fdc951cd46104f63922188 /arch/hexagon | |
| parent | f184c5caa983940305b37f428a6bfc22105235e4 (diff) | |
| download | linux-fsl-qoriq-af7f032dba8ccf7ee430a48656d25565672a6074.tar.xz | |
arm: zynq: timer: Remove unnecessary register write
Acknowedging an interrupt requires to read the interrupt register
only. The write was only required to work around a bug in
the QEMU implementation of the TTC, which is fixed.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Tested-by: Josh Cartwright <josh.cartwright@ni.com>
Diffstat (limited to 'arch/hexagon')
0 files changed, 0 insertions, 0 deletions