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authorLinus Torvalds <torvalds@g5.osdl.org>2005-10-29 04:09:26 (GMT)
committerLinus Torvalds <torvalds@g5.osdl.org>2005-10-29 04:09:26 (GMT)
commit8a212ab6b8a4ccc6f3c3d1beba5f92655c576404 (patch)
tree525271129ff9c692defdd20566f1f7203b18ff24 /arch/ia64/kernel/patch.c
parent1f419cadff55f548e7356ffebdb9e1b5a8c22275 (diff)
parent0e1f60609258e18ec0a0477c646101212822d387 (diff)
downloadlinux-fsl-qoriq-8a212ab6b8a4ccc6f3c3d1beba5f92655c576404.tar.xz
Merge branch 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6
Diffstat (limited to 'arch/ia64/kernel/patch.c')
-rw-r--r--arch/ia64/kernel/patch.c16
1 files changed, 12 insertions, 4 deletions
diff --git a/arch/ia64/kernel/patch.c b/arch/ia64/kernel/patch.c
index 367804a..6a4ac7d 100644
--- a/arch/ia64/kernel/patch.c
+++ b/arch/ia64/kernel/patch.c
@@ -64,22 +64,30 @@ ia64_patch (u64 insn_addr, u64 mask, u64 val)
void
ia64_patch_imm64 (u64 insn_addr, u64 val)
{
- ia64_patch(insn_addr,
+ /* The assembler may generate offset pointing to either slot 1
+ or slot 2 for a long (2-slot) instruction, occupying slots 1
+ and 2. */
+ insn_addr &= -16UL;
+ ia64_patch(insn_addr + 2,
0x01fffefe000UL, ( ((val & 0x8000000000000000UL) >> 27) /* bit 63 -> 36 */
| ((val & 0x0000000000200000UL) << 0) /* bit 21 -> 21 */
| ((val & 0x00000000001f0000UL) << 6) /* bit 16 -> 22 */
| ((val & 0x000000000000ff80UL) << 20) /* bit 7 -> 27 */
| ((val & 0x000000000000007fUL) << 13) /* bit 0 -> 13 */));
- ia64_patch(insn_addr - 1, 0x1ffffffffffUL, val >> 22);
+ ia64_patch(insn_addr + 1, 0x1ffffffffffUL, val >> 22);
}
void
ia64_patch_imm60 (u64 insn_addr, u64 val)
{
- ia64_patch(insn_addr,
+ /* The assembler may generate offset pointing to either slot 1
+ or slot 2 for a long (2-slot) instruction, occupying slots 1
+ and 2. */
+ insn_addr &= -16UL;
+ ia64_patch(insn_addr + 2,
0x011ffffe000UL, ( ((val & 0x0800000000000000UL) >> 23) /* bit 59 -> 36 */
| ((val & 0x00000000000fffffUL) << 13) /* bit 0 -> 13 */));
- ia64_patch(insn_addr - 1, 0x1fffffffffcUL, val >> 18);
+ ia64_patch(insn_addr + 1, 0x1fffffffffcUL, val >> 18);
}
/*