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author | Florian Fainelli <florian@openwrt.org> | 2012-06-18 10:07:51 (GMT) |
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committer | Ralf Baechle <ralf@linux-mips.org> | 2012-08-17 08:57:28 (GMT) |
commit | 5a6704454a68ab6e27e4fc5b82818a8c5733bf29 (patch) | |
tree | 4b27c7f37bfe26985ff08ad09368e375cfe6dc89 /arch/m32r | |
parent | c54de490a2e4e74164f747925ff05c00dfa153cd (diff) | |
download | linux-fsl-qoriq-5a6704454a68ab6e27e4fc5b82818a8c5733bf29.tar.xz |
MIPS: BCM63xx: Fix SPI message control register handling for BCM6338/6348.
BCM6338 and BCM6348 have a message control register width of 8 bits, instead
of 16-bits like what the SPI driver assumes right now. Also the SPI message
type shift value of 14 is actually 6 for these SoCs.
This resulted in transmit FIFO corruption because we were writing 16-bits
to an 8-bits wide register, thus spanning on the first byte of the transmit
FIFO, which had already been filed in bcm63xx_spi_fill_txrx_fifo().
Fix this by passing the message control register width and message type
shift through platform data back to the SPI driver so that it can use
it properly.
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: grant.likely@secretlab.ca
Cc: spi-devel-general@lists.sourceforge.net
Cc: jonas.gorski@gmail.com
Patchwork: https://patchwork.linux-mips.org/patch/3983/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/m32r')
0 files changed, 0 insertions, 0 deletions