diff options
| author | Arnd Bergmann <arnd@arndb.de> | 2013-04-09 13:50:59 (GMT) |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2013-04-09 14:01:23 (GMT) |
| commit | 835f9c38bbb4498c3d43b7466964bdadbb1fd244 (patch) | |
| tree | ade5aec66bc7ddb97048c4f141932de0f93369b9 /arch/m68k/include/asm/MC68328.h | |
| parent | f5f29151588744ea2e283971cb0ad403ee04e3e2 (diff) | |
| parent | a937536b868b8369b98967929045f1df54234323 (diff) | |
| download | linux-fsl-qoriq-835f9c38bbb4498c3d43b7466964bdadbb1fd244.tar.xz | |
Merge tag 'v3.9-rc3' into next/multiplatform
Linux 3.9-rc3
Conflicts:
arch/arm/Kconfig
arch/arm/mach-spear/spear3xx.c
arch/arm/plat-spear/Kconfig
This is a dependency for ux500/multiplatform
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/m68k/include/asm/MC68328.h')
| -rw-r--r-- | arch/m68k/include/asm/MC68328.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/m68k/include/asm/MC68328.h b/arch/m68k/include/asm/MC68328.h index a337e56..4ebf098 100644 --- a/arch/m68k/include/asm/MC68328.h +++ b/arch/m68k/include/asm/MC68328.h @@ -293,7 +293,7 @@ /* * Here go the bitmasks themselves */ -#define IMR_MSPIM (1 << SPIM _IRQ_NUM) /* Mask SPI Master interrupt */ +#define IMR_MSPIM (1 << SPIM_IRQ_NUM) /* Mask SPI Master interrupt */ #define IMR_MTMR2 (1 << TMR2_IRQ_NUM) /* Mask Timer 2 interrupt */ #define IMR_MUART (1 << UART_IRQ_NUM) /* Mask UART interrupt */ #define IMR_MWDT (1 << WDT_IRQ_NUM) /* Mask Watchdog Timer interrupt */ @@ -327,7 +327,7 @@ #define IWR_ADDR 0xfffff308 #define IWR LONG_REF(IWR_ADDR) -#define IWR_SPIM (1 << SPIM _IRQ_NUM) /* SPI Master interrupt */ +#define IWR_SPIM (1 << SPIM_IRQ_NUM) /* SPI Master interrupt */ #define IWR_TMR2 (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */ #define IWR_UART (1 << UART_IRQ_NUM) /* UART interrupt */ #define IWR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */ @@ -357,7 +357,7 @@ #define ISR_ADDR 0xfffff30c #define ISR LONG_REF(ISR_ADDR) -#define ISR_SPIM (1 << SPIM _IRQ_NUM) /* SPI Master interrupt */ +#define ISR_SPIM (1 << SPIM_IRQ_NUM) /* SPI Master interrupt */ #define ISR_TMR2 (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */ #define ISR_UART (1 << UART_IRQ_NUM) /* UART interrupt */ #define ISR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */ @@ -391,7 +391,7 @@ #define IPR_ADDR 0xfffff310 #define IPR LONG_REF(IPR_ADDR) -#define IPR_SPIM (1 << SPIM _IRQ_NUM) /* SPI Master interrupt */ +#define IPR_SPIM (1 << SPIM_IRQ_NUM) /* SPI Master interrupt */ #define IPR_TMR2 (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */ #define IPR_UART (1 << UART_IRQ_NUM) /* UART interrupt */ #define IPR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */ @@ -757,7 +757,7 @@ /* 'EZ328-compatible definitions */ #define TCN_ADDR TCN1_ADDR -#define TCN TCN +#define TCN TCN1 /* * Timer Unit 1 and 2 Status Registers |