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| author | Greg Ungerer <gerg@uclinux.org> | 2012-07-15 12:01:08 (GMT) |
|---|---|---|
| committer | Greg Ungerer <gerg@uclinux.org> | 2012-09-27 13:33:48 (GMT) |
| commit | 660b73e356a63d67231aab49d23e83b1a5a9ec87 (patch) | |
| tree | f829ff36a22a50939125f9ae7b99170cca9079a6 /arch/m68k/include/asm/m525xsim.h | |
| parent | e1e362dc074c2981e7f78d26bf38a4f14be52ecd (diff) | |
| download | linux-fsl-qoriq-660b73e356a63d67231aab49d23e83b1a5a9ec87.tar.xz | |
m68knommu: make ColdFire watchdog register definitions absolute addresses
Make all definitions of the ColdFire Software watchdog registers absolute
addresses. Currently some are relative to the MBAR peripheral region.
The various ColdFire parts use different methods to address the internal
registers, some are absolute, some are relative to peripheral regions
which can be mapped at different address ranges (such as the MBAR and IPSBAR
registers). We don't want to deal with this in the code when we are
accessing these registers, so make all register definitions the absolute
address - factoring out whether it is an offset into a peripheral region.
This makes them all consistently defined, and reduces the occasional bugs
caused by inconsistent definition of the register addresses.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k/include/asm/m525xsim.h')
| -rw-r--r-- | arch/m68k/include/asm/m525xsim.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/m68k/include/asm/m525xsim.h b/arch/m68k/include/asm/m525xsim.h index 05876cc..b0fccd9 100644 --- a/arch/m68k/include/asm/m525xsim.h +++ b/arch/m68k/include/asm/m525xsim.h @@ -28,8 +28,8 @@ */ #define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */ #define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */ -#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */ -#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ +#define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */ +#define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog srv */ #define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/ #define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */ #define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */ |