diff options
| author | Greg Ungerer <gerg@uclinux.org> | 2012-09-14 05:36:02 (GMT) |
|---|---|---|
| committer | Greg Ungerer <gerg@uclinux.org> | 2012-09-27 13:33:51 (GMT) |
| commit | 1419ea3b34db3e3cf5d6bedb3f913ed814022030 (patch) | |
| tree | bd70f5315a28884f89f5425038cdcaec5dd0a20e /arch/m68k/include/asm/m5272sim.h | |
| parent | c986a3d520395604ca29a7fb9fca60a455abcc44 (diff) | |
| download | linux-fsl-qoriq-1419ea3b34db3e3cf5d6bedb3f913ed814022030.tar.xz | |
m68knommu: make ColdFire Chip Select register definitions absolute addresses
Make all definitions of the ColdFire Chip Select registers absolute addresses.
Currently some are relative to the MBAR peripheral region.
The various ColdFire parts use different methods to address the internal
registers, some are absolute, some are relative to peripheral regions
which can be mapped at different address ranges (such as the MBAR and IPSBAR
registers). We don't want to deal with this in the code when we are
accessing these registers, so make all register definitions the absolute
address - factoring out whether it is an offset into a peripheral region.
This makes them all consistently defined, and reduces the occasional bugs
caused by inconsistent definition of the register addresses.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k/include/asm/m5272sim.h')
| -rw-r--r-- | arch/m68k/include/asm/m5272sim.h | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/arch/m68k/include/asm/m5272sim.h b/arch/m68k/include/asm/m5272sim.h index 2b21787..3a5319e 100644 --- a/arch/m68k/include/asm/m5272sim.h +++ b/arch/m68k/include/asm/m5272sim.h @@ -42,22 +42,22 @@ #define MCFSIM_WCR (MCF_MBAR + 0x288) /* Watchdog counter */ #define MCFSIM_WER (MCF_MBAR + 0x28c) /* Watchdog event */ -#define MCFSIM_CSBR0 0x40 /* CS0 Base Address (r/w) */ -#define MCFSIM_CSOR0 0x44 /* CS0 Option (r/w) */ -#define MCFSIM_CSBR1 0x48 /* CS1 Base Address (r/w) */ -#define MCFSIM_CSOR1 0x4c /* CS1 Option (r/w) */ -#define MCFSIM_CSBR2 0x50 /* CS2 Base Address (r/w) */ -#define MCFSIM_CSOR2 0x54 /* CS2 Option (r/w) */ -#define MCFSIM_CSBR3 0x58 /* CS3 Base Address (r/w) */ -#define MCFSIM_CSOR3 0x5c /* CS3 Option (r/w) */ -#define MCFSIM_CSBR4 0x60 /* CS4 Base Address (r/w) */ -#define MCFSIM_CSOR4 0x64 /* CS4 Option (r/w) */ -#define MCFSIM_CSBR5 0x68 /* CS5 Base Address (r/w) */ -#define MCFSIM_CSOR5 0x6c /* CS5 Option (r/w) */ -#define MCFSIM_CSBR6 0x70 /* CS6 Base Address (r/w) */ -#define MCFSIM_CSOR6 0x74 /* CS6 Option (r/w) */ -#define MCFSIM_CSBR7 0x78 /* CS7 Base Address (r/w) */ -#define MCFSIM_CSOR7 0x7c /* CS7 Option (r/w) */ +#define MCFSIM_CSBR0 (MCF_MBAR + 0x40) /* CS0 Base Address */ +#define MCFSIM_CSOR0 (MCF_MBAR + 0x44) /* CS0 Option */ +#define MCFSIM_CSBR1 (MCF_MBAR + 0x48) /* CS1 Base Address */ +#define MCFSIM_CSOR1 (MCF_MBAR + 0x4c) /* CS1 Option */ +#define MCFSIM_CSBR2 (MCF_MBAR + 0x50) /* CS2 Base Address */ +#define MCFSIM_CSOR2 (MCF_MBAR + 0x54) /* CS2 Option */ +#define MCFSIM_CSBR3 (MCF_MBAR + 0x58) /* CS3 Base Address */ +#define MCFSIM_CSOR3 (MCF_MBAR + 0x5c) /* CS3 Option */ +#define MCFSIM_CSBR4 (MCF_MBAR + 0x60) /* CS4 Base Address */ +#define MCFSIM_CSOR4 (MCF_MBAR + 0x64) /* CS4 Option */ +#define MCFSIM_CSBR5 (MCF_MBAR + 0x68) /* CS5 Base Address */ +#define MCFSIM_CSOR5 (MCF_MBAR + 0x6c) /* CS5 Option */ +#define MCFSIM_CSBR6 (MCF_MBAR + 0x70) /* CS6 Base Address */ +#define MCFSIM_CSOR6 (MCF_MBAR + 0x74) /* CS6 Option */ +#define MCFSIM_CSBR7 (MCF_MBAR + 0x78) /* CS7 Base Address */ +#define MCFSIM_CSOR7 (MCF_MBAR + 0x7c) /* CS7 Option */ #define MCFSIM_SDCR 0x180 /* SDRAM Configuration (r/w) */ #define MCFSIM_SDTR 0x184 /* SDRAM Timing (r/w) */ |