diff options
| author | John Crispin <blogic@openwrt.org> | 2012-08-16 11:39:57 (GMT) |
|---|---|---|
| committer | John Crispin <blogic@openwrt.org> | 2012-08-22 22:08:17 (GMT) |
| commit | 61fa969f27ec58296544bf94d058f3aa704cb8d9 (patch) | |
| tree | b4c8597b9b6fc758be9a42f3940cec7b2893f888 /arch/mips/include/asm | |
| parent | fea7a08acb13524b47711625eebea40a0ede69a0 (diff) | |
| download | linux-fsl-qoriq-61fa969f27ec58296544bf94d058f3aa704cb8d9.tar.xz | |
MIPS: lantiq: split up IRQ IM ranges
Up to now all our SoCs had the 5 IM ranges in a consecutive order. To accomodate
the SVIP we need to support IM ranges that are scattered inside the register range.
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4237/
Diffstat (limited to 'arch/mips/include/asm')
| -rw-r--r-- | arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h | 2 | ||||
| -rw-r--r-- | arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h | 2 |
2 files changed, 4 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h b/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h index 318f982..c6b63a4 100644 --- a/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h +++ b/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h @@ -20,4 +20,6 @@ #define MIPS_CPU_TIMER_IRQ 7 +#define MAX_IM 5 + #endif /* _FALCON_IRQ__ */ diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h index aa0b3b8..5eadfe5 100644 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h @@ -21,4 +21,6 @@ #define MIPS_CPU_TIMER_IRQ 7 +#define MAX_IM 5 + #endif |