diff options
author | David Daney <david.daney@cavium.com> | 2013-07-29 22:07:04 (GMT) |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2013-08-26 13:31:53 (GMT) |
commit | 62597c60816967100243338421782469b831563d (patch) | |
tree | 7029119ef0fd8e75c08dd60cee277cb26328aba4 /arch/mips/mm/c-octeon.c | |
parent | 4723b20a381ae488d845f3e041ef1dd71c6f40f8 (diff) | |
download | linux-fsl-qoriq-62597c60816967100243338421782469b831563d.tar.xz |
MIPS: OCTEON: Set L1 cache parameters for OCTEON3 CPUs.
Signed-off-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5638/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm/c-octeon.c')
-rw-r--r-- | arch/mips/mm/c-octeon.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c index a0bcdbb..729e770 100644 --- a/arch/mips/mm/c-octeon.c +++ b/arch/mips/mm/c-octeon.c @@ -224,6 +224,20 @@ static void probe_octeon(void) c->options |= MIPS_CPU_PREFETCH; break; + case CPU_CAVIUM_OCTEON3: + c->icache.linesz = 128; + c->icache.sets = 16; + c->icache.ways = 39; + c->icache.flags |= MIPS_CACHE_VTAG; + icache_size = c->icache.sets * c->icache.ways * c->icache.linesz; + + c->dcache.linesz = 128; + c->dcache.ways = 32; + c->dcache.sets = 8; + dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz; + c->options |= MIPS_CPU_PREFETCH; + break; + default: panic("Unsupported Cavium Networks CPU type"); break; |