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authorLinus Torvalds <torvalds@linux-foundation.org>2013-09-19 17:52:25 (GMT)
committerLinus Torvalds <torvalds@linux-foundation.org>2013-09-19 17:52:25 (GMT)
commitf05f8198e415151bc6f8369c93e25befcafe8026 (patch)
treef063f67a13db617268209e5c5792a9bf8e7113c9 /arch/mips/mm/c-octeon.c
parente9ff04dd94d46c817bbb103531cdef6e7bd5d022 (diff)
parent66b10574b86046dbe10c4326e43964a79e0b3a64 (diff)
downloadlinux-fsl-qoriq-f05f8198e415151bc6f8369c93e25befcafe8026.tar.xz
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle: - Minor updates and fixes to the Octeon ethernet driver in staging - A fix to VGA_MAP_MEM() for 64 bit platforms - Fix a workaround for 74K/1074K processors - The symlink arch/mips/boot/dts/include/dt-bindings was pointing to a a file with a name ending in \n. I think this may have been caused by a git bug with with patches sent by email - A build fix for VGA console on BCM1480-based systems - Fix PCI device access via "/sys/bus/pci/.../resource0" or similar work for Alchemy platforms - Fix potential data leak on MIPS R5 cores. This doesn't add proper support for any R5 features, just ensures a kernel without such support will be secure to run - Adding a macros for the CP0 Config5 register to be used by the R5 fix - Make get_cycles() actually return something useful where possible This also requires a preparatory patch for performance sake - Fix a warning about the use of smp_processor_id() in preemptible code. Again this includes a preparatory patch adding the infrastructure to be used by the actual patch - Finally remove pointless one-line comment * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: MIPS: Fix invalid symbolic link file MIPS: PCI: pci-bcm1480: Include missing vt.h header MIPS: Disable usermode switching of the FR bit for MIPS R5 CPUs. MIPS: Add MIPS R5 config5 register. MIPS: PCI: Use pci_resource_to_user to map pci memory space properly MIPS: 74K/1074K: Correct erratum workaround. MIPS: Cleanup CP0 PRId and CP1 FPIR register access masks MIPS: Remove useless comment about kprobe from arch/mips/Makefile MIPS: Fix VGA_MAP_MEM macro. MIPS: Reimplement get_cycles(). MIPS: Optimize current_cpu_type() for better code. MIPS: Fix accessing to per-cpu data when flushing the cache MIPS: Provide nice way to access boot CPU's data. staging: octeon-ethernet: rgmii: enable interrupts that we can handle staging: octeon-ethernet: remove skb alloc failure warnings staging: octeon-ethernet: make dropped packets to consume NAPI budget
Diffstat (limited to 'arch/mips/mm/c-octeon.c')
-rw-r--r--arch/mips/mm/c-octeon.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c
index 729e770..c8efdb5 100644
--- a/arch/mips/mm/c-octeon.c
+++ b/arch/mips/mm/c-octeon.c
@@ -19,6 +19,7 @@
#include <asm/bootinfo.h>
#include <asm/cacheops.h>
#include <asm/cpu-features.h>
+#include <asm/cpu-type.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/r4kcache.h>
@@ -186,9 +187,10 @@ static void probe_octeon(void)
unsigned long dcache_size;
unsigned int config1;
struct cpuinfo_mips *c = &current_cpu_data;
+ int cputype = current_cpu_type();
config1 = read_c0_config1();
- switch (c->cputype) {
+ switch (cputype) {
case CPU_CAVIUM_OCTEON:
case CPU_CAVIUM_OCTEON_PLUS:
c->icache.linesz = 2 << ((config1 >> 19) & 7);
@@ -199,7 +201,7 @@ static void probe_octeon(void)
c->icache.sets * c->icache.ways * c->icache.linesz;
c->icache.waybit = ffs(icache_size / c->icache.ways) - 1;
c->dcache.linesz = 128;
- if (c->cputype == CPU_CAVIUM_OCTEON_PLUS)
+ if (cputype == CPU_CAVIUM_OCTEON_PLUS)
c->dcache.sets = 2; /* CN5XXX has two Dcache sets */
else
c->dcache.sets = 1; /* CN3XXX has one Dcache set */