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| author | Chenhui Zhao <chenhui.zhao@freescale.com> | 2015-07-08 10:10:55 (GMT) |
|---|---|---|
| committer | Zhengxiong Jin <Jason.Jin@freescale.com> | 2015-07-09 07:17:22 (GMT) |
| commit | 7a6dba419338704f39798b30c0ee8203d779db6e (patch) | |
| tree | a6ca74e6433a39031dbeac9dc6444643c6e489cb /arch/mips/pmcs-msp71xx | |
| parent | 4e614179832ee15663e3486770263f9b3309ac7d (diff) | |
| download | linux-fsl-qoriq-7a6dba419338704f39798b30c0ee8203d779db6e.tar.xz | |
arm: ls1021a: change the order of setting PMC interrupt registers
In deep sleep process, set interrupt status and polarity registers
before enabling PMC interrupts. It is more stable, especially on
ls1021a-twr board.
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Change-Id: I8305e25a76f0bcc636b58178495165c915ac3c1a
Reviewed-on: http://git.am.freescale.net:8181/39478
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Diffstat (limited to 'arch/mips/pmcs-msp71xx')
0 files changed, 0 insertions, 0 deletions