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| author | Nicolas Pitre <nicolas.pitre@linaro.org> | 2012-07-18 20:41:16 (GMT) |
|---|---|---|
| committer | Nicolas Pitre <nicolas.pitre@linaro.org> | 2013-05-29 19:50:35 (GMT) |
| commit | 2f2df895ee3518fbef28dfa6736dfd1e1c04ee1c (patch) | |
| tree | cca1f6645e733c760da0837e71d323a68be2111e /arch/mips/power | |
| parent | 13eae144ec754ab64521891d2cffc3156f6f083f (diff) | |
| download | linux-fsl-qoriq-2f2df895ee3518fbef28dfa6736dfd1e1c04ee1c.tar.xz | |
ARM: vexpress/dcscb: do not hardcode number of CPUs per cluster
If 4 CPUs are assumed, the A15x1-A7x1 model configuration would never
shut down the initial cluster as the 0xf reset bit mask will never be
observed. Let's construct this mask based on the provided information
in the DCSCB config register for the number of CPUs per cluster.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Pawel Moll <pawel.moll@arm.com>
Diffstat (limited to 'arch/mips/power')
0 files changed, 0 insertions, 0 deletions