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authorJeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com>2009-04-07 20:34:16 (GMT)
committerJeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com>2009-04-07 20:34:16 (GMT)
commit38f4b8c0da01ae7cd9b93386842ce272d6fde9ab (patch)
tree3c8c52201aac038094bfea7efdd0984a8f62045e /arch/mips
parenta811454027352c762e0d5bba1b1d8f7d26bf96ae (diff)
parent8e2c4f2844c0e8dcdfe312e5f2204854ca8532c6 (diff)
downloadlinux-fsl-qoriq-38f4b8c0da01ae7cd9b93386842ce272d6fde9ab.tar.xz
Merge commit 'origin/master' into for-linus/xen/master
* commit 'origin/master': (4825 commits) Fix build errors due to CONFIG_BRANCH_TRACER=y parport: Use the PCI IRQ if offered tty: jsm cleanups Adjust path to gpio headers KGDB_SERIAL_CONSOLE check for module Change KCONFIG name tty: Blackin CTS/RTS Change hardware flow control from poll to interrupt driven Add support for the MAX3100 SPI UART. lanana: assign a device name and numbering for MAX3100 serqt: initial clean up pass for tty side tty: Use the generic RS485 ioctl on CRIS tty: Correct inline types for tty_driver_kref_get() splice: fix deadlock in splicing to file nilfs2: support nanosecond timestamp nilfs2: introduce secondary super block nilfs2: simplify handling of active state of segments nilfs2: mark minor flag for checkpoint created by internal operation nilfs2: clean up sketch file nilfs2: super block operations fix endian bug ... Conflicts: arch/x86/include/asm/thread_info.h arch/x86/lguest/boot.c drivers/xen/manage.c
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/Kconfig14
-rw-r--r--arch/mips/Makefile6
-rw-r--r--arch/mips/alchemy/Kconfig2
-rw-r--r--arch/mips/alchemy/common/gpio.c203
-rw-r--r--arch/mips/alchemy/common/platform.c30
-rw-r--r--arch/mips/alchemy/devboards/pb1200/platform.c14
-rw-r--r--arch/mips/cavium-octeon/Makefile2
-rw-r--r--arch/mips/cavium-octeon/flash_setup.c2
-rw-r--r--arch/mips/cavium-octeon/octeon-irq.c2
-rw-r--r--arch/mips/cobalt/irq.c1
-rw-r--r--arch/mips/emma/markeins/irq.c51
-rw-r--r--arch/mips/emma/markeins/platform.c3
-rw-r--r--arch/mips/include/asm/cpu.h3
-rw-r--r--arch/mips/include/asm/ftrace.h1
-rw-r--r--arch/mips/include/asm/hazards.h4
-rw-r--r--arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h49
-rw-r--r--arch/mips/include/asm/mach-au1x00/gpio.h70
-rw-r--r--arch/mips/include/asm/mach-bcm47xx/gpio.h20
-rw-r--r--arch/mips/include/asm/mach-ip27/topology.h1
-rw-r--r--arch/mips/include/asm/mips-boards/generic.h2
-rw-r--r--arch/mips/include/asm/smp-ops.h2
-rw-r--r--arch/mips/include/asm/spinlock.h10
-rw-r--r--arch/mips/include/asm/txx9/ndfmc.h30
-rw-r--r--arch/mips/include/asm/txx9/rbtx4939.h9
-rw-r--r--arch/mips/include/asm/txx9/tx4938.h1
-rw-r--r--arch/mips/include/asm/txx9/tx4939.h2
-rw-r--r--arch/mips/include/asm/types.h8
-rw-r--r--arch/mips/include/asm/unistd.h18
-rw-r--r--arch/mips/jazz/irq.c1
-rw-r--r--arch/mips/jazz/jazzdma.c3
-rw-r--r--arch/mips/kernel/cevt-bcm1480.c1
-rw-r--r--arch/mips/kernel/cevt-sb1250.c1
-rw-r--r--arch/mips/kernel/cpu-probe.c21
-rw-r--r--arch/mips/kernel/i8253.c2
-rw-r--r--arch/mips/kernel/i8259.c1
-rw-r--r--arch/mips/kernel/irq-msc01.c6
-rw-r--r--arch/mips/kernel/irq_cpu.c3
-rw-r--r--arch/mips/kernel/linux32.c6
-rw-r--r--arch/mips/kernel/process.c2
-rw-r--r--arch/mips/kernel/scall32-o32.S2
-rw-r--r--arch/mips/kernel/scall64-64.S2
-rw-r--r--arch/mips/kernel/scall64-n32.S2
-rw-r--r--arch/mips/kernel/scall64-o32.S2
-rw-r--r--arch/mips/kernel/setup.c3
-rw-r--r--arch/mips/kernel/smp-up.c14
-rw-r--r--arch/mips/kernel/smp.c2
-rw-r--r--arch/mips/kernel/traps.c3
-rw-r--r--arch/mips/lasat/interrupt.c1
-rw-r--r--arch/mips/lemote/lm2e/irq.c1
-rw-r--r--arch/mips/mm/c-r4k.c17
-rw-r--r--arch/mips/mm/highmem.c11
-rw-r--r--arch/mips/mm/init.c3
-rw-r--r--arch/mips/mm/ioremap.c9
-rw-r--r--arch/mips/mm/tlbex.c8
-rw-r--r--arch/mips/mti-malta/malta-init.c2
-rw-r--r--arch/mips/nxp/pnx833x/common/platform.c12
-rw-r--r--arch/mips/nxp/pnx8550/common/platform.c8
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_usb.c8
-rw-r--r--arch/mips/sgi-ip27/ip27-berr.c2
-rw-r--r--arch/mips/sgi-ip27/ip27-nmi.c6
-rw-r--r--arch/mips/sgi-ip27/ip27-smp.c2
-rw-r--r--arch/mips/sgi-ip32/ip32-irq.c65
-rw-r--r--arch/mips/sgi-ip32/ip32-memory.c2
-rw-r--r--arch/mips/sibyte/bcm1480/irq.c2
-rw-r--r--arch/mips/sibyte/sb1250/irq.c2
-rw-r--r--arch/mips/sni/a20r.c2
-rw-r--r--arch/mips/sni/pcimt.c2
-rw-r--r--arch/mips/sni/pcit.c4
-rw-r--r--arch/mips/sni/rm200.c5
-rw-r--r--arch/mips/txx9/Kconfig1
-rw-r--r--arch/mips/txx9/generic/setup.c21
-rw-r--r--arch/mips/txx9/generic/setup_tx4938.c21
-rw-r--r--arch/mips/txx9/generic/setup_tx4939.c17
-rw-r--r--arch/mips/txx9/rbtx4938/setup.c2
-rw-r--r--arch/mips/txx9/rbtx4939/setup.c161
-rw-r--r--arch/mips/vr41xx/common/irq.c1
76 files changed, 690 insertions, 345 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 206cb79..998e5db 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -77,7 +77,6 @@ config MIPS_COBALT
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_LITTLE_ENDIAN
- select GENERIC_HARDIRQS_NO__DO_IRQ
config MACH_DECSTATION
bool "DECstations"
@@ -132,11 +131,10 @@ config MACH_JAZZ
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
select SYS_SUPPORTS_100HZ
- select GENERIC_HARDIRQS_NO__DO_IRQ
help
This a family of machines based on the MIPS R4030 chipset which was
used by several vendors to build RISC/os and Windows NT workstations.
- Members include the Acer PICA, MIPS Magnum 4000, MIPS Millenium and
+ Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
Olivetti M700-10 workstations.
config LASAT
@@ -154,7 +152,6 @@ config LASAT
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL if BROKEN
select SYS_SUPPORTS_LITTLE_ENDIAN
- select GENERIC_HARDIRQS_NO__DO_IRQ
config LEMOTE_FULONG
bool "Lemote Fulong mini-PC"
@@ -175,7 +172,6 @@ config LEMOTE_FULONG
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_HIGHMEM
select SYS_HAS_EARLY_PRINTK
- select GENERIC_HARDIRQS_NO__DO_IRQ
select GENERIC_ISA_DMA_SUPPORT_BROKEN
select CPU_HAS_WB
help
@@ -250,7 +246,6 @@ config MACH_VR41XX
select CEVT_R4K
select CSRC_R4K
select SYS_HAS_CPU_VR41XX
- select GENERIC_HARDIRQS_NO__DO_IRQ
config NXP_STB220
bool "NXP STB220 board"
@@ -364,7 +359,6 @@ config SGI_IP27
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_NUMA
select SYS_SUPPORTS_SMP
- select GENERIC_HARDIRQS_NO__DO_IRQ
help
This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
workstations. To compile a Linux kernel that runs on these, say Y
@@ -563,7 +557,6 @@ config MIKROTIK_RB532
select CEVT_R4K
select CSRC_R4K
select DMA_NONCOHERENT
- select GENERIC_HARDIRQS_NO__DO_IRQ
select HW_HAS_PCI
select IRQ_CPU
select SYS_HAS_CPU_MIPS32_R1
@@ -700,8 +693,7 @@ config SCHED_OMIT_FRAME_POINTER
default y
config GENERIC_HARDIRQS_NO__DO_IRQ
- bool
- default n
+ def_bool y
#
# Select some configuration options automatically based on user selections.
@@ -920,7 +912,6 @@ config SOC_PNX833X
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_BIG_ENDIAN
- select GENERIC_HARDIRQS_NO__DO_IRQ
select GENERIC_GPIO
select CPU_MIPSR2_IRQ_VI
@@ -939,7 +930,6 @@ config SOC_PNX8550
select SYS_HAS_CPU_MIPS32_R1
select SYS_HAS_EARLY_PRINTK
select SYS_SUPPORTS_32BIT_KERNEL
- select GENERIC_HARDIRQS_NO__DO_IRQ
select GENERIC_GPIO
config SWAP_IO_SPACE
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 22dab2e..8d544c7 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -720,11 +720,17 @@ ifdef CONFIG_MIPS32_O32
$(Q)$(MAKE) $(build)=. missing-syscalls EXTRA_CFLAGS="-mabi=32"
endif
+install:
+ $(Q)install -D -m 755 vmlinux $(INSTALL_PATH)/vmlinux-$(KERNELRELEASE)
+ $(Q)install -D -m 644 .config $(INSTALL_PATH)/config-$(KERNELRELEASE)
+ $(Q)install -D -m 644 System.map $(INSTALL_PATH)/System.map-$(KERNELRELEASE)
+
archclean:
@$(MAKE) $(clean)=arch/mips/boot
@$(MAKE) $(clean)=arch/mips/lasat
define archhelp
+ echo ' install - install kernel into $(INSTALL_PATH)'
echo ' vmlinux.ecoff - ECOFF boot image'
echo ' vmlinux.bin - Raw binary boot image'
echo ' vmlinux.srec - SREC boot image'
diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig
index 7f8ef13..8128aeb 100644
--- a/arch/mips/alchemy/Kconfig
+++ b/arch/mips/alchemy/Kconfig
@@ -134,4 +134,4 @@ config SOC_AU1X00
select SYS_HAS_CPU_MIPS32_R1
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_APM_EMULATION
- select GENERIC_HARDIRQS_NO__DO_IRQ
+ select ARCH_REQUIRE_GPIOLIB
diff --git a/arch/mips/alchemy/common/gpio.c b/arch/mips/alchemy/common/gpio.c
index e660ddd..91a9c44 100644
--- a/arch/mips/alchemy/common/gpio.c
+++ b/arch/mips/alchemy/common/gpio.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2007, OpenWrt.org, Florian Fainelli <florian@openwrt.org>
+ * Copyright (C) 2007-2009, OpenWrt.org, Florian Fainelli <florian@openwrt.org>
* Architecture specific GPIO support
*
* This program is free software; you can redistribute it and/or modify it
@@ -27,122 +27,175 @@
* others have a second one : GPIO2
*/
+#include <linux/kernel.h>
#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/gpio.h>
-#define gpio1 sys
-#if !defined(CONFIG_SOC_AU1000)
-
-static struct au1x00_gpio2 *const gpio2 = (struct au1x00_gpio2 *) GPIO2_BASE;
-#define GPIO2_OUTPUT_ENABLE_MASK 0x00010000
+struct au1000_gpio_chip {
+ struct gpio_chip chip;
+ void __iomem *regbase;
+};
-static int au1xxx_gpio2_read(unsigned gpio)
+#if !defined(CONFIG_SOC_AU1000)
+static int au1000_gpio2_get(struct gpio_chip *chip, unsigned offset)
{
- gpio -= AU1XXX_GPIO_BASE;
- return ((gpio2->pinstate >> gpio) & 0x01);
+ u32 mask = 1 << offset;
+ struct au1000_gpio_chip *gpch;
+
+ gpch = container_of(chip, struct au1000_gpio_chip, chip);
+ return readl(gpch->regbase + AU1000_GPIO2_ST) & mask;
}
-static void au1xxx_gpio2_write(unsigned gpio, int value)
+static void au1000_gpio2_set(struct gpio_chip *chip,
+ unsigned offset, int value)
{
- gpio -= AU1XXX_GPIO_BASE;
+ u32 mask = ((GPIO2_OUT_EN_MASK << offset) | (!!value << offset));
+ struct au1000_gpio_chip *gpch;
+ unsigned long flags;
+
+ gpch = container_of(chip, struct au1000_gpio_chip, chip);
- gpio2->output = (GPIO2_OUTPUT_ENABLE_MASK << gpio) | ((!!value) << gpio);
+ local_irq_save(flags);
+ writel(mask, gpch->regbase + AU1000_GPIO2_OUT);
+ local_irq_restore(flags);
}
-static int au1xxx_gpio2_direction_input(unsigned gpio)
+static int au1000_gpio2_direction_input(struct gpio_chip *chip, unsigned offset)
{
- gpio -= AU1XXX_GPIO_BASE;
- gpio2->dir &= ~(0x01 << gpio);
+ u32 mask = 1 << offset;
+ u32 tmp;
+ struct au1000_gpio_chip *gpch;
+ unsigned long flags;
+
+ gpch = container_of(chip, struct au1000_gpio_chip, chip);
+
+ local_irq_save(flags);
+ tmp = readl(gpch->regbase + AU1000_GPIO2_DIR);
+ tmp &= ~mask;
+ writel(tmp, gpch->regbase + AU1000_GPIO2_DIR);
+ local_irq_restore(flags);
+
return 0;
}
-static int au1xxx_gpio2_direction_output(unsigned gpio, int value)
+static int au1000_gpio2_direction_output(struct gpio_chip *chip,
+ unsigned offset, int value)
{
- gpio -= AU1XXX_GPIO_BASE;
- gpio2->dir |= 0x01 << gpio;
- gpio2->output = (GPIO2_OUTPUT_ENABLE_MASK << gpio) | ((!!value) << gpio);
+ u32 mask = 1 << offset;
+ u32 out_mask = ((GPIO2_OUT_EN_MASK << offset) | (!!value << offset));
+ u32 tmp;
+ struct au1000_gpio_chip *gpch;
+ unsigned long flags;
+
+ gpch = container_of(chip, struct au1000_gpio_chip, chip);
+
+ local_irq_save(flags);
+ tmp = readl(gpch->regbase + AU1000_GPIO2_DIR);
+ tmp |= mask;
+ writel(tmp, gpch->regbase + AU1000_GPIO2_DIR);
+ writel(out_mask, gpch->regbase + AU1000_GPIO2_OUT);
+ local_irq_restore(flags);
+
return 0;
}
-
#endif /* !defined(CONFIG_SOC_AU1000) */
-static int au1xxx_gpio1_read(unsigned gpio)
+static int au1000_gpio1_get(struct gpio_chip *chip, unsigned offset)
{
- return (gpio1->pinstaterd >> gpio) & 0x01;
+ u32 mask = 1 << offset;
+ struct au1000_gpio_chip *gpch;
+
+ gpch = container_of(chip, struct au1000_gpio_chip, chip);
+ return readl(gpch->regbase + AU1000_GPIO1_ST) & mask;
}
-static void au1xxx_gpio1_write(unsigned gpio, int value)
+static void au1000_gpio1_set(struct gpio_chip *chip,
+ unsigned offset, int value)
{
+ u32 mask = 1 << offset;
+ u32 reg_offset;
+ struct au1000_gpio_chip *gpch;
+ unsigned long flags;
+
+ gpch = container_of(chip, struct au1000_gpio_chip, chip);
+
if (value)
- gpio1->outputset = (0x01 << gpio);
+ reg_offset = AU1000_GPIO1_OUT;
else
- /* Output a zero */
- gpio1->outputclr = (0x01 << gpio);
-}
+ reg_offset = AU1000_GPIO1_CLR;
-static int au1xxx_gpio1_direction_input(unsigned gpio)
-{
- gpio1->pininputen = (0x01 << gpio);
- return 0;
+ local_irq_save(flags);
+ writel(mask, gpch->regbase + reg_offset);
+ local_irq_restore(flags);
}
-static int au1xxx_gpio1_direction_output(unsigned gpio, int value)
+static int au1000_gpio1_direction_input(struct gpio_chip *chip, unsigned offset)
{
- gpio1->trioutclr = (0x01 & gpio);
- au1xxx_gpio1_write(gpio, value);
+ u32 mask = 1 << offset;
+ struct au1000_gpio_chip *gpch;
+
+ gpch = container_of(chip, struct au1000_gpio_chip, chip);
+ writel(mask, gpch->regbase + AU1000_GPIO1_ST);
+
return 0;
}
-int au1xxx_gpio_get_value(unsigned gpio)
+static int au1000_gpio1_direction_output(struct gpio_chip *chip,
+ unsigned offset, int value)
{
- if (gpio >= AU1XXX_GPIO_BASE)
-#if defined(CONFIG_SOC_AU1000)
- return 0;
-#else
- return au1xxx_gpio2_read(gpio);
-#endif
- else
- return au1xxx_gpio1_read(gpio);
-}
-EXPORT_SYMBOL(au1xxx_gpio_get_value);
+ u32 mask = 1 << offset;
+ struct au1000_gpio_chip *gpch;
-void au1xxx_gpio_set_value(unsigned gpio, int value)
-{
- if (gpio >= AU1XXX_GPIO_BASE)
-#if defined(CONFIG_SOC_AU1000)
- ;
-#else
- au1xxx_gpio2_write(gpio, value);
-#endif
- else
- au1xxx_gpio1_write(gpio, value);
-}
-EXPORT_SYMBOL(au1xxx_gpio_set_value);
+ gpch = container_of(chip, struct au1000_gpio_chip, chip);
-int au1xxx_gpio_direction_input(unsigned gpio)
-{
- if (gpio >= AU1XXX_GPIO_BASE)
-#if defined(CONFIG_SOC_AU1000)
- return -ENODEV;
-#else
- return au1xxx_gpio2_direction_input(gpio);
-#endif
+ writel(mask, gpch->regbase + AU1000_GPIO1_TRI_OUT);
+ au1000_gpio1_set(chip, offset, value);
- return au1xxx_gpio1_direction_input(gpio);
+ return 0;
}
-EXPORT_SYMBOL(au1xxx_gpio_direction_input);
-int au1xxx_gpio_direction_output(unsigned gpio, int value)
+struct au1000_gpio_chip au1000_gpio_chip[] = {
+ [0] = {
+ .regbase = (void __iomem *)SYS_BASE,
+ .chip = {
+ .label = "au1000-gpio1",
+ .direction_input = au1000_gpio1_direction_input,
+ .direction_output = au1000_gpio1_direction_output,
+ .get = au1000_gpio1_get,
+ .set = au1000_gpio1_set,
+ .base = 0,
+ .ngpio = 32,
+ },
+ },
+#if !defined(CONFIG_SOC_AU1000)
+ [1] = {
+ .regbase = (void __iomem *)GPIO2_BASE,
+ .chip = {
+ .label = "au1000-gpio2",
+ .direction_input = au1000_gpio2_direction_input,
+ .direction_output = au1000_gpio2_direction_output,
+ .get = au1000_gpio2_get,
+ .set = au1000_gpio2_set,
+ .base = AU1XXX_GPIO_BASE,
+ .ngpio = 32,
+ },
+ },
+#endif
+};
+
+static int __init au1000_gpio_init(void)
{
- if (gpio >= AU1XXX_GPIO_BASE)
-#if defined(CONFIG_SOC_AU1000)
- return -ENODEV;
-#else
- return au1xxx_gpio2_direction_output(gpio, value);
+ gpiochip_add(&au1000_gpio_chip[0].chip);
+#if !defined(CONFIG_SOC_AU1000)
+ gpiochip_add(&au1000_gpio_chip[1].chip);
#endif
- return au1xxx_gpio1_direction_output(gpio, value);
+ return 0;
}
-EXPORT_SYMBOL(au1xxx_gpio_direction_output);
+arch_initcall(au1000_gpio_init);
+
diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c
index 5c76c64..117f99f 100644
--- a/arch/mips/alchemy/common/platform.c
+++ b/arch/mips/alchemy/common/platform.c
@@ -80,14 +80,14 @@ static struct resource au1xxx_usb_ohci_resources[] = {
};
/* The dmamask must be set for OHCI to work */
-static u64 ohci_dmamask = DMA_32BIT_MASK;
+static u64 ohci_dmamask = DMA_BIT_MASK(32);
static struct platform_device au1xxx_usb_ohci_device = {
.name = "au1xxx-ohci",
.id = 0,
.dev = {
.dma_mask = &ohci_dmamask,
- .coherent_dma_mask = DMA_32BIT_MASK,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
},
.num_resources = ARRAY_SIZE(au1xxx_usb_ohci_resources),
.resource = au1xxx_usb_ohci_resources,
@@ -109,14 +109,14 @@ static struct resource au1100_lcd_resources[] = {
}
};
-static u64 au1100_lcd_dmamask = DMA_32BIT_MASK;
+static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32);
static struct platform_device au1100_lcd_device = {
.name = "au1100-lcd",
.id = 0,
.dev = {
.dma_mask = &au1100_lcd_dmamask,
- .coherent_dma_mask = DMA_32BIT_MASK,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
},
.num_resources = ARRAY_SIZE(au1100_lcd_resources),
.resource = au1100_lcd_resources,
@@ -138,14 +138,14 @@ static struct resource au1xxx_usb_ehci_resources[] = {
},
};
-static u64 ehci_dmamask = DMA_32BIT_MASK;
+static u64 ehci_dmamask = DMA_BIT_MASK(32);
static struct platform_device au1xxx_usb_ehci_device = {
.name = "au1xxx-ehci",
.id = 0,
.dev = {
.dma_mask = &ehci_dmamask,
- .coherent_dma_mask = DMA_32BIT_MASK,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
},
.num_resources = ARRAY_SIZE(au1xxx_usb_ehci_resources),
.resource = au1xxx_usb_ehci_resources,
@@ -165,14 +165,14 @@ static struct resource au1xxx_usb_gdt_resources[] = {
},
};
-static u64 udc_dmamask = DMA_32BIT_MASK;
+static u64 udc_dmamask = DMA_BIT_MASK(32);
static struct platform_device au1xxx_usb_gdt_device = {
.name = "au1xxx-udc",
.id = 0,
.dev = {
.dma_mask = &udc_dmamask,
- .coherent_dma_mask = DMA_32BIT_MASK,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
},
.num_resources = ARRAY_SIZE(au1xxx_usb_gdt_resources),
.resource = au1xxx_usb_gdt_resources,
@@ -192,14 +192,14 @@ static struct resource au1xxx_usb_otg_resources[] = {
},
};
-static u64 uoc_dmamask = DMA_32BIT_MASK;
+static u64 uoc_dmamask = DMA_BIT_MASK(32);
static struct platform_device au1xxx_usb_otg_device = {
.name = "au1xxx-uoc",
.id = 0,
.dev = {
.dma_mask = &uoc_dmamask,
- .coherent_dma_mask = DMA_32BIT_MASK,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
},
.num_resources = ARRAY_SIZE(au1xxx_usb_otg_resources),
.resource = au1xxx_usb_otg_resources,
@@ -218,20 +218,20 @@ static struct resource au1200_lcd_resources[] = {
}
};
-static u64 au1200_lcd_dmamask = DMA_32BIT_MASK;
+static u64 au1200_lcd_dmamask = DMA_BIT_MASK(32);
static struct platform_device au1200_lcd_device = {
.name = "au1200-lcd",
.id = 0,
.dev = {
.dma_mask = &au1200_lcd_dmamask,
- .coherent_dma_mask = DMA_32BIT_MASK,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
},
.num_resources = ARRAY_SIZE(au1200_lcd_resources),
.resource = au1200_lcd_resources,
};
-static u64 au1xxx_mmc_dmamask = DMA_32BIT_MASK;
+static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32);
extern struct au1xmmc_platform_data au1xmmc_platdata[2];
@@ -263,7 +263,7 @@ static struct platform_device au1200_mmc0_device = {
.id = 0,
.dev = {
.dma_mask = &au1xxx_mmc_dmamask,
- .coherent_dma_mask = DMA_32BIT_MASK,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &au1xmmc_platdata[0],
},
.num_resources = ARRAY_SIZE(au1200_mmc0_resources),
@@ -299,7 +299,7 @@ static struct platform_device au1200_mmc1_device = {
.id = 1,
.dev = {
.dma_mask = &au1xxx_mmc_dmamask,
- .coherent_dma_mask = DMA_32BIT_MASK,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &au1xmmc_platdata[1],
},
.num_resources = ARRAY_SIZE(au1200_mmc1_resources),
diff --git a/arch/mips/alchemy/devboards/pb1200/platform.c b/arch/mips/alchemy/devboards/pb1200/platform.c
index 9530329..b93dff4 100644
--- a/arch/mips/alchemy/devboards/pb1200/platform.c
+++ b/arch/mips/alchemy/devboards/pb1200/platform.c
@@ -22,6 +22,7 @@
#include <linux/init.h>
#include <linux/leds.h>
#include <linux/platform_device.h>
+#include <linux/smc91x.h>
#include <asm/mach-au1x00/au1xxx.h>
#include <asm/mach-au1x00/au1100_mmc.h>
@@ -118,19 +119,25 @@ static struct resource ide_resources[] = {
}
};
-static u64 ide_dmamask = DMA_32BIT_MASK;
+static u64 ide_dmamask = DMA_BIT_MASK(32);
static struct platform_device ide_device = {
.name = "au1200-ide",
.id = 0,
.dev = {
.dma_mask = &ide_dmamask,
- .coherent_dma_mask = DMA_32BIT_MASK,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
},
.num_resources = ARRAY_SIZE(ide_resources),
.resource = ide_resources
};
+static struct smc91x_platdata smc_data = {
+ .flags = SMC91X_NOWAIT | SMC91X_USE_16BIT,
+ .leda = RPC_LED_100_10,
+ .ledb = RPC_LED_TX_RX,
+};
+
static struct resource smc91c111_resources[] = {
[0] = {
.name = "smc91x-regs",
@@ -146,6 +153,9 @@ static struct resource smc91c111_resources[] = {
};
static struct platform_device smc91c111_device = {
+ .dev = {
+ .platform_data = &smc_data,
+ },
.name = "smc91x",
.id = -1,
.num_resources = ARRAY_SIZE(smc91c111_resources),
diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
index 1c2a7fa..d6903c3 100644
--- a/arch/mips/cavium-octeon/Makefile
+++ b/arch/mips/cavium-octeon/Makefile
@@ -14,3 +14,5 @@ obj-y += dma-octeon.o flash_setup.o
obj-y += octeon-memcpy.o
obj-$(CONFIG_SMP) += smp.o
+
+EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/cavium-octeon/flash_setup.c b/arch/mips/cavium-octeon/flash_setup.c
index 553d36c..008f657 100644
--- a/arch/mips/cavium-octeon/flash_setup.c
+++ b/arch/mips/cavium-octeon/flash_setup.c
@@ -57,7 +57,7 @@ static int __init flash_init(void)
flash_map.bankwidth = 1;
flash_map.virt = ioremap(flash_map.phys, flash_map.size);
pr_notice("Bootbus flash: Setting flash for %luMB flash at "
- "0x%08lx\n", flash_map.size >> 20, flash_map.phys);
+ "0x%08llx\n", flash_map.size >> 20, flash_map.phys);
simple_map_init(&flash_map);
mymtd = do_map_probe("cfi_probe", &flash_map);
if (mymtd) {
diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c
index fc72984..1c19af8 100644
--- a/arch/mips/cavium-octeon/octeon-irq.c
+++ b/arch/mips/cavium-octeon/octeon-irq.c
@@ -31,7 +31,7 @@ static void octeon_irq_core_ack(unsigned int irq)
static void octeon_irq_core_eoi(unsigned int irq)
{
- irq_desc_t *desc = irq_desc + irq;
+ struct irq_desc *desc = irq_desc + irq;
unsigned int bit = irq - OCTEON_IRQ_SW0;
/*
* If an IRQ is being processed while we are disabling it the
diff --git a/arch/mips/cobalt/irq.c b/arch/mips/cobalt/irq.c
index ac4fb91..cb9bf82 100644
--- a/arch/mips/cobalt/irq.c
+++ b/arch/mips/cobalt/irq.c
@@ -47,7 +47,6 @@ asmlinkage void plat_irq_dispatch(void)
static struct irqaction cascade = {
.handler = no_action,
- .mask = CPU_MASK_NONE,
.name = "cascade",
};
diff --git a/arch/mips/emma/markeins/irq.c b/arch/mips/emma/markeins/irq.c
index c2583ec..43828ae 100644
--- a/arch/mips/emma/markeins/irq.c
+++ b/arch/mips/emma/markeins/irq.c
@@ -80,9 +80,9 @@ void emma2rh_irq_init(void)
u32 i;
for (i = 0; i < NUM_EMMA2RH_IRQ; i++)
- set_irq_chip_and_handler(EMMA2RH_IRQ_BASE + i,
- &emma2rh_irq_controller,
- handle_level_irq);
+ set_irq_chip_and_handler_name(EMMA2RH_IRQ_BASE + i,
+ &emma2rh_irq_controller,
+ handle_level_irq, "level");
}
static void emma2rh_sw_irq_enable(unsigned int irq)
@@ -120,9 +120,9 @@ void emma2rh_sw_irq_init(void)
u32 i;
for (i = 0; i < NUM_EMMA2RH_IRQ_SW; i++)
- set_irq_chip_and_handler(EMMA2RH_SW_IRQ_BASE + i,
- &emma2rh_sw_irq_controller,
- handle_level_irq);
+ set_irq_chip_and_handler_name(EMMA2RH_SW_IRQ_BASE + i,
+ &emma2rh_sw_irq_controller,
+ handle_level_irq, "level");
}
static void emma2rh_gpio_irq_enable(unsigned int irq)
@@ -149,37 +149,28 @@ static void emma2rh_gpio_irq_disable(unsigned int irq)
static void emma2rh_gpio_irq_ack(unsigned int irq)
{
- u32 reg;
-
irq -= EMMA2RH_GPIO_IRQ_BASE;
emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq));
-
- reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
- reg &= ~(1 << irq);
- emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
}
-static void emma2rh_gpio_irq_end(unsigned int irq)
+static void emma2rh_gpio_irq_mask_ack(unsigned int irq)
{
u32 reg;
- if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
-
- irq -= EMMA2RH_GPIO_IRQ_BASE;
+ irq -= EMMA2RH_GPIO_IRQ_BASE;
+ emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq));
- reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
- reg |= 1 << irq;
- emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
- }
+ reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
+ reg &= ~(1 << irq);
+ emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
}
struct irq_chip emma2rh_gpio_irq_controller = {
.name = "emma2rh_gpio_irq",
.ack = emma2rh_gpio_irq_ack,
.mask = emma2rh_gpio_irq_disable,
- .mask_ack = emma2rh_gpio_irq_ack,
+ .mask_ack = emma2rh_gpio_irq_mask_ack,
.unmask = emma2rh_gpio_irq_enable,
- .end = emma2rh_gpio_irq_end,
};
void emma2rh_gpio_irq_init(void)
@@ -187,14 +178,14 @@ void emma2rh_gpio_irq_init(void)
u32 i;
for (i = 0; i < NUM_EMMA2RH_IRQ_GPIO; i++)
- set_irq_chip(EMMA2RH_GPIO_IRQ_BASE + i,
- &emma2rh_gpio_irq_controller);
+ set_irq_chip_and_handler_name(EMMA2RH_GPIO_IRQ_BASE + i,
+ &emma2rh_gpio_irq_controller,
+ handle_edge_irq, "edge");
}
static struct irqaction irq_cascade = {
.handler = no_action,
.flags = 0,
- .mask = CPU_MASK_NONE,
.name = "cascade",
.dev_id = NULL,
.next = NULL,
@@ -213,8 +204,7 @@ void emma2rh_irq_dispatch(void)
emma2rh_in32(EMMA2RH_BHIF_INT_EN_0);
#ifdef EMMA2RH_SW_CASCADE
- if (intStatus &
- (1 << ((EMMA2RH_SW_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) {
+ if (intStatus & (1UL << EMMA2RH_SW_CASCADE)) {
u32 swIntStatus;
swIntStatus = emma2rh_in32(EMMA2RH_BHIF_SW_INT)
& emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
@@ -225,6 +215,8 @@ void emma2rh_irq_dispatch(void)
}
}
}
+ /* Skip S/W interrupt */
+ intStatus &= ~(1UL << EMMA2RH_SW_CASCADE);
#endif
for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
@@ -238,8 +230,7 @@ void emma2rh_irq_dispatch(void)
emma2rh_in32(EMMA2RH_BHIF_INT_EN_1);
#ifdef EMMA2RH_GPIO_CASCADE
- if (intStatus &
- (1 << ((EMMA2RH_GPIO_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) {
+ if (intStatus & (1UL << (EMMA2RH_GPIO_CASCADE % 32))) {
u32 gpioIntStatus;
gpioIntStatus = emma2rh_in32(EMMA2RH_GPIO_INT_ST)
& emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
@@ -250,6 +241,8 @@ void emma2rh_irq_dispatch(void)
}
}
}
+ /* Skip GPIO interrupt */
+ intStatus &= ~(1UL << (EMMA2RH_GPIO_CASCADE % 32));
#endif
for (i = 32, bitmask = 1; i < 64; i++, bitmask <<= 1) {
diff --git a/arch/mips/emma/markeins/platform.c b/arch/mips/emma/markeins/platform.c
index d5f47e4..80ae12e 100644
--- a/arch/mips/emma/markeins/platform.c
+++ b/arch/mips/emma/markeins/platform.c
@@ -110,6 +110,7 @@ struct platform_device i2c_emma_devices[] = {
static struct plat_serial8250_port platform_serial_ports[] = {
[0] = {
.membase= (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR0_BASE + 3),
+ .mapbase = EMMA2RH_PFUR0_BASE + 3,
.irq = EMMA2RH_IRQ_PFUR0,
.uartclk = EMMA2RH_SERIAL_CLOCK,
.regshift = 4,
@@ -117,6 +118,7 @@ static struct plat_serial8250_port platform_serial_ports[] = {
.flags = EMMA2RH_SERIAL_FLAGS,
}, [1] = {
.membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR1_BASE + 3),
+ .mapbase = EMMA2RH_PFUR1_BASE + 3,
.irq = EMMA2RH_IRQ_PFUR1,
.uartclk = EMMA2RH_SERIAL_CLOCK,
.regshift = 4,
@@ -124,6 +126,7 @@ static struct plat_serial8250_port platform_serial_ports[] = {
.flags = EMMA2RH_SERIAL_FLAGS,
}, [2] = {
.membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR2_BASE + 3),
+ .mapbase = EMMA2RH_PFUR2_BASE + 3,
.irq = EMMA2RH_IRQ_PFUR2,
.uartclk = EMMA2RH_SERIAL_CLOCK,
.regshift = 4,
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index c018727..3bdc0e3 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -209,8 +209,7 @@ enum cpu_type_enum {
* MIPS32 class processors
*/
CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
- CPU_AU1000, CPU_AU1100, CPU_AU1200, CPU_AU1210, CPU_AU1250, CPU_AU1500,
- CPU_AU1550, CPU_PR4450, CPU_BCM3302, CPU_BCM4710,
+ CPU_ALCHEMY, CPU_PR4450, CPU_BCM3302, CPU_BCM4710,
/*
* MIPS64 class processors
diff --git a/arch/mips/include/asm/ftrace.h b/arch/mips/include/asm/ftrace.h
new file mode 100644
index 0000000..40a8c17
--- /dev/null
+++ b/arch/mips/include/asm/ftrace.h
@@ -0,0 +1 @@
+/* empty */
diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h
index 134e1fc..a12d971 100644
--- a/arch/mips/include/asm/hazards.h
+++ b/arch/mips/include/asm/hazards.h
@@ -87,7 +87,7 @@ do { \
: "=r" (tmp)); \
} while (0)
-#elif defined(CONFIG_CPU_MIPSR1)
+#elif defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MACH_ALCHEMY)
/*
* These are slightly complicated by the fact that we guarantee R1 kernels to
@@ -139,7 +139,7 @@ do { \
} while (0)
#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
- defined(CONFIG_CPU_R5500)
+ defined(CONFIG_CPU_R5500) || defined(CONFIG_MACH_ALCHEMY)
/*
* R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
diff --git a/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h b/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
new file mode 100644
index 0000000..d5df0ca
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
@@ -0,0 +1,49 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __ASM_MACH_AU1X00_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_AU1X00_CPU_FEATURE_OVERRIDES_H
+
+#define cpu_has_tlb 1
+#define cpu_has_4kex 1
+#define cpu_has_3k_cache 0
+#define cpu_has_4k_cache 1
+#define cpu_has_tx39_cache 0
+#define cpu_has_fpu 0
+#define cpu_has_counter 1
+#define cpu_has_watch 1
+#define cpu_has_divec 1
+#define cpu_has_vce 0
+#define cpu_has_cache_cdex_p 0
+#define cpu_has_cache_cdex_s 0
+#define cpu_has_mcheck 1
+#define cpu_has_ejtag 1
+#define cpu_has_llsc 1
+#define cpu_has_mips16 0
+#define cpu_has_mdmx 0
+#define cpu_has_mips3d 0
+#define cpu_has_smartmips 0
+#define cpu_has_vtag_icache 0
+#define cpu_has_dc_aliases 0
+#define cpu_has_ic_fills_f_dc 1
+#define cpu_has_mips32r1 1
+#define cpu_has_mips32r2 0
+#define cpu_has_mips64r1 0
+#define cpu_has_mips64r2 0
+#define cpu_has_dsp 0
+#define cpu_has_mipsmt 0
+#define cpu_has_userlocal 0
+#define cpu_has_nofpuex 0
+#define cpu_has_64bits 0
+#define cpu_has_64bit_zero_reg 0
+#define cpu_has_vint 0
+#define cpu_has_veic 0
+#define cpu_has_inclusive_pcaches 0
+
+#define cpu_dcache_line_size() 32
+#define cpu_icache_line_size() 32
+
+#endif /* __ASM_MACH_AU1X00_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-au1x00/gpio.h b/arch/mips/include/asm/mach-au1x00/gpio.h
index 2dc61e0..34d9b72 100644
--- a/arch/mips/include/asm/mach-au1x00/gpio.h
+++ b/arch/mips/include/asm/mach-au1x00/gpio.h
@@ -5,65 +5,29 @@
#define AU1XXX_GPIO_BASE 200
-struct au1x00_gpio2 {
- u32 dir;
- u32 reserved;
- u32 output;
- u32 pinstate;
- u32 inten;
- u32 enable;
-};
+/* GPIO bank 1 offsets */
+#define AU1000_GPIO1_TRI_OUT 0x0100
+#define AU1000_GPIO1_OUT 0x0108
+#define AU1000_GPIO1_ST 0x0110
+#define AU1000_GPIO1_CLR 0x010C
-extern int au1xxx_gpio_get_value(unsigned gpio);
-extern void au1xxx_gpio_set_value(unsigned gpio, int value);
-extern int au1xxx_gpio_direction_input(unsigned gpio);
-extern int au1xxx_gpio_direction_output(unsigned gpio, int value);
+/* GPIO bank 2 offsets */
+#define AU1000_GPIO2_DIR 0x00
+#define AU1000_GPIO2_RSVD 0x04
+#define AU1000_GPIO2_OUT 0x08
+#define AU1000_GPIO2_ST 0x0C
+#define AU1000_GPIO2_INT 0x10
+#define AU1000_GPIO2_EN 0x14
+#define GPIO2_OUT_EN_MASK 0x00010000
-/* Wrappers for the arch-neutral GPIO API */
+#define gpio_to_irq(gpio) NULL
-static inline int gpio_request(unsigned gpio, const char *label)
-{
- /* Not yet implemented */
- return 0;
-}
+#define gpio_get_value __gpio_get_value
+#define gpio_set_value __gpio_set_value
-static inline void gpio_free(unsigned gpio)
-{
- /* Not yet implemented */
-}
+#define gpio_cansleep __gpio_cansleep
-static inline int gpio_direction_input(unsigned gpio)
-{
- return au1xxx_gpio_direction_input(gpio);
-}
-
-static inline int gpio_direction_output(unsigned gpio, int value)
-{
- return au1xxx_gpio_direction_output(gpio, value);
-}
-
-static inline int gpio_get_value(unsigned gpio)
-{
- return au1xxx_gpio_get_value(gpio);
-}
-
-static inline void gpio_set_value(unsigned gpio, int value)
-{
- au1xxx_gpio_set_value(gpio, value);
-}
-
-static inline int gpio_to_irq(unsigned gpio)
-{
- return gpio;
-}
-
-static inline int irq_to_gpio(unsigned irq)
-{
- return irq;
-}
-
-/* For cansleep */
#include <asm-generic/gpio.h>
#endif /* _AU1XXX_GPIO_H_ */
diff --git a/arch/mips/include/asm/mach-bcm47xx/gpio.h b/arch/mips/include/asm/mach-bcm47xx/gpio.h
index d8ff4cd..1784fde 100644
--- a/arch/mips/include/asm/mach-bcm47xx/gpio.h
+++ b/arch/mips/include/asm/mach-bcm47xx/gpio.h
@@ -31,24 +31,28 @@ static inline void gpio_set_value(unsigned gpio, int value)
static inline int gpio_direction_input(unsigned gpio)
{
- return ssb_gpio_outen(&ssb_bcm47xx, 1 << gpio, 0);
+ ssb_gpio_outen(&ssb_bcm47xx, 1 << gpio, 0);
+ return 0;
}
static inline int gpio_direction_output(unsigned gpio, int value)
{
- return ssb_gpio_outen(&ssb_bcm47xx, 1 << gpio, 1 << gpio);
+ ssb_gpio_outen(&ssb_bcm47xx, 1 << gpio, 1 << gpio);
+ return 0;
}
-static int gpio_intmask(unsigned gpio, int value)
+static inline int gpio_intmask(unsigned gpio, int value)
{
- return ssb_gpio_intmask(&ssb_bcm47xx, 1 << gpio,
- value ? 1 << gpio : 0);
+ ssb_gpio_intmask(&ssb_bcm47xx, 1 << gpio,
+ value ? 1 << gpio : 0);
+ return 0;
}
-static int gpio_polarity(unsigned gpio, int value)
+static inline int gpio_polarity(unsigned gpio, int value)
{
- return ssb_gpio_polarity(&ssb_bcm47xx, 1 << gpio,
- value ? 1 << gpio : 0);
+ ssb_gpio_polarity(&ssb_bcm47xx, 1 << gpio,
+ value ? 1 << gpio : 0);
+ return 0;
}
diff --git a/arch/mips/include/asm/mach-ip27/topology.h b/arch/mips/include/asm/mach-ip27/topology.h
index 55d4815..0754723 100644
--- a/arch/mips/include/asm/mach-ip27/topology.h
+++ b/arch/mips/include/asm/mach-ip27/topology.h
@@ -26,7 +26,6 @@ extern struct cpuinfo_ip27 sn_cpu_info[NR_CPUS];
#define parent_node(node) (node)
#define node_to_cpumask(node) (hub_data(node)->h_cpus)
#define cpumask_of_node(node) (&hub_data(node)->h_cpus)
-#define node_to_first_cpu(node) (cpumask_first(cpumask_of_node(node)))
struct pci_bus;
extern int pcibus_to_node(struct pci_bus *);
diff --git a/arch/mips/include/asm/mips-boards/generic.h b/arch/mips/include/asm/mips-boards/generic.h
index 7f0b034..c0da1a8 100644
--- a/arch/mips/include/asm/mips-boards/generic.h
+++ b/arch/mips/include/asm/mips-boards/generic.h
@@ -71,8 +71,6 @@
#define MIPS_REVISION_CORID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 10) & 0x3f)
-extern int mips_revision_corid;
-
#define MIPS_REVISION_SCON_OTHER 0
#define MIPS_REVISION_SCON_SOCITSC 1
#define MIPS_REVISION_SCON_SOCITSCP 2
diff --git a/arch/mips/include/asm/smp-ops.h b/arch/mips/include/asm/smp-ops.h
index 43c207e7..64ffc02 100644
--- a/arch/mips/include/asm/smp-ops.h
+++ b/arch/mips/include/asm/smp-ops.h
@@ -15,6 +15,8 @@
#include <linux/cpumask.h>
+struct task_struct;
+
struct plat_smp_ops {
void (*send_ipi_single)(int cpu, unsigned int action);
void (*send_ipi_mask)(cpumask_t mask, unsigned int action);
diff --git a/arch/mips/include/asm/spinlock.h b/arch/mips/include/asm/spinlock.h
index 0884947..5b60a09 100644
--- a/arch/mips/include/asm/spinlock.h
+++ b/arch/mips/include/asm/spinlock.h
@@ -76,7 +76,7 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
"2: \n"
" .subsection 2 \n"
"4: andi %[ticket], %[ticket], 0x1fff \n"
- "5: sll %[ticket], 5 \n"
+ " sll %[ticket], 5 \n"
" \n"
"6: bnez %[ticket], 6b \n"
" subu %[ticket], 1 \n"
@@ -85,7 +85,7 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
" andi %[ticket], %[ticket], 0x1fff \n"
" beq %[ticket], %[my_ticket], 2b \n"
" subu %[ticket], %[my_ticket], %[ticket] \n"
- " b 5b \n"
+ " b 4b \n"
" subu %[ticket], %[ticket], 1 \n"
" .previous \n"
" .set pop \n"
@@ -113,7 +113,7 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
" ll %[ticket], %[ticket_ptr] \n"
" \n"
"4: andi %[ticket], %[ticket], 0x1fff \n"
- "5: sll %[ticket], 5 \n"
+ " sll %[ticket], 5 \n"
" \n"
"6: bnez %[ticket], 6b \n"
" subu %[ticket], 1 \n"
@@ -122,7 +122,7 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
" andi %[ticket], %[ticket], 0x1fff \n"
" beq %[ticket], %[my_ticket], 2b \n"
" subu %[ticket], %[my_ticket], %[ticket] \n"
- " b 5b \n"
+ " b 4b \n"
" subu %[ticket], %[ticket], 1 \n"
" .previous \n"
" .set pop \n"
@@ -480,6 +480,8 @@ static inline int __raw_write_trylock(raw_rwlock_t *rw)
return ret;
}
+#define __raw_read_lock_flags(lock, flags) __raw_read_lock(lock)
+#define __raw_write_lock_flags(lock, flags) __raw_write_lock(lock)
#define _raw_spin_relax(lock) cpu_relax()
#define _raw_read_relax(lock) cpu_relax()
diff --git a/arch/mips/include/asm/txx9/ndfmc.h b/arch/mips/include/asm/txx9/ndfmc.h
new file mode 100644
index 0000000..fa67f3d
--- /dev/null
+++ b/arch/mips/include/asm/txx9/ndfmc.h
@@ -0,0 +1,30 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * (C) Copyright TOSHIBA CORPORATION 2007
+ */
+#ifndef __ASM_TXX9_NDFMC_H
+#define __ASM_TXX9_NDFMC_H
+
+#define NDFMC_PLAT_FLAG_USE_BSPRT 0x01
+#define NDFMC_PLAT_FLAG_NO_RSTR 0x02
+#define NDFMC_PLAT_FLAG_HOLDADD 0x04
+#define NDFMC_PLAT_FLAG_DUMMYWRITE 0x08
+
+struct txx9ndfmc_platform_data {
+ unsigned int shift;
+ unsigned int gbus_clock;
+ unsigned int hold; /* hold time in nanosecond */
+ unsigned int spw; /* strobe pulse width in nanosecond */
+ unsigned int flags;
+ unsigned char ch_mask; /* available channel bitmask */
+ unsigned char wp_mask; /* write-protect bitmask */
+ unsigned char wide_mask; /* 16bit-nand bitmask */
+};
+
+void txx9_ndfmc_init(unsigned long baseaddr,
+ const struct txx9ndfmc_platform_data *plat_data);
+
+#endif /* __ASM_TXX9_NDFMC_H */
diff --git a/arch/mips/include/asm/txx9/rbtx4939.h b/arch/mips/include/asm/txx9/rbtx4939.h
index 1acf428..e517899 100644
--- a/arch/mips/include/asm/txx9/rbtx4939.h
+++ b/arch/mips/include/asm/txx9/rbtx4939.h
@@ -130,4 +130,13 @@
void rbtx4939_prom_init(void);
void rbtx4939_irq_setup(void);
+struct mtd_partition;
+struct map_info;
+struct rbtx4939_flash_data {
+ unsigned int width;
+ unsigned int nr_parts;
+ struct mtd_partition *parts;
+ void (*map_init)(struct map_info *map);
+};
+
#endif /* __ASM_TXX9_RBTX4939_H */
diff --git a/arch/mips/include/asm/txx9/tx4938.h b/arch/mips/include/asm/txx9/tx4938.h
index 0b06815..cd8bc20 100644
--- a/arch/mips/include/asm/txx9/tx4938.h
+++ b/arch/mips/include/asm/txx9/tx4938.h
@@ -291,6 +291,7 @@ int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot);
void tx4938_setup_pcierr_irq(void);
void tx4938_irq_init(void);
void tx4938_mtd_init(int ch);
+void tx4938_ndfmc_init(unsigned int hold, unsigned int spw);
struct tx4938ide_platform_info {
/*
diff --git a/arch/mips/include/asm/txx9/tx4939.h b/arch/mips/include/asm/txx9/tx4939.h
index 964ef7e..f02c50b 100644
--- a/arch/mips/include/asm/txx9/tx4939.h
+++ b/arch/mips/include/asm/txx9/tx4939.h
@@ -542,5 +542,7 @@ int tx4939_irq(void);
void tx4939_mtd_init(int ch);
void tx4939_ata_init(void);
void tx4939_rtc_init(void);
+void tx4939_ndfmc_init(unsigned int hold, unsigned int spw,
+ unsigned char ch_mask, unsigned char wide_mask);
#endif /* __ASM_TXX9_TX4939_H */
diff --git a/arch/mips/include/asm/types.h b/arch/mips/include/asm/types.h
index bcbb8d6..7956e69 100644
--- a/arch/mips/include/asm/types.h
+++ b/arch/mips/include/asm/types.h
@@ -4,12 +4,18 @@
* for more details.
*
* Copyright (C) 1994, 1995, 1996, 1999 by Ralf Baechle
+ * Copyright (C) 2008 Wind River Systems,
+ * written by Ralf Baechle
* Copyright (C) 1999 Silicon Graphics, Inc.
*/
#ifndef _ASM_TYPES_H
#define _ASM_TYPES_H
-#if _MIPS_SZLONG == 64
+/*
+ * We don't use int-l64.h for the kernel anymore but still use it for
+ * userspace to avoid code changes.
+ */
+#if (_MIPS_SZLONG == 64) && !defined(__KERNEL__)
# include <asm-generic/int-l64.h>
#else
# include <asm-generic/int-ll64.h>
diff --git a/arch/mips/include/asm/unistd.h b/arch/mips/include/asm/unistd.h
index a73e153..4000501 100644
--- a/arch/mips/include/asm/unistd.h
+++ b/arch/mips/include/asm/unistd.h
@@ -350,16 +350,18 @@
#define __NR_dup3 (__NR_Linux + 327)
#define __NR_pipe2 (__NR_Linux + 328)
#define __NR_inotify_init1 (__NR_Linux + 329)
+#define __NR_preadv (__NR_Linux + 330)
+#define __NR_pwritev (__NR_Linux + 331)
/*
* Offset of the last Linux o32 flavoured syscall
*/
-#define __NR_Linux_syscalls 329
+#define __NR_Linux_syscalls 331
#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
#define __NR_O32_Linux 4000
-#define __NR_O32_Linux_syscalls 329
+#define __NR_O32_Linux_syscalls 331
#if _MIPS_SIM == _MIPS_SIM_ABI64
@@ -656,16 +658,18 @@
#define __NR_dup3 (__NR_Linux + 286)
#define __NR_pipe2 (__NR_Linux + 287)
#define __NR_inotify_init1 (__NR_Linux + 288)
+#define __NR_preadv (__NR_Linux + 289)
+#define __NR_pwritev (__NR_Linux + 290)
/*
* Offset of the last Linux 64-bit flavoured syscall
*/
-#define __NR_Linux_syscalls 288
+#define __NR_Linux_syscalls 290
#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
#define __NR_64_Linux 5000
-#define __NR_64_Linux_syscalls 288
+#define __NR_64_Linux_syscalls 290
#if _MIPS_SIM == _MIPS_SIM_NABI32
@@ -966,16 +970,18 @@
#define __NR_dup3 (__NR_Linux + 290)
#define __NR_pipe2 (__NR_Linux + 291)
#define __NR_inotify_init1 (__NR_Linux + 292)
+#define __NR_preadv (__NR_Linux + 293)
+#define __NR_pwritev (__NR_Linux + 294)
/*
* Offset of the last N32 flavoured syscall
*/
-#define __NR_Linux_syscalls 292
+#define __NR_Linux_syscalls 294
#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
#define __NR_N32_Linux 6000
-#define __NR_N32_Linux_syscalls 292
+#define __NR_N32_Linux_syscalls 294
#ifdef __KERNEL__
diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c
index 03965cb..d9b6a5b 100644
--- a/arch/mips/jazz/irq.c
+++ b/arch/mips/jazz/irq.c
@@ -134,7 +134,6 @@ static irqreturn_t r4030_timer_interrupt(int irq, void *dev_id)
static struct irqaction r4030_timer_irqaction = {
.handler = r4030_timer_interrupt,
.flags = IRQF_DISABLED,
- .mask = CPU_MASK_CPU0,
.name = "R4030 timer",
};
diff --git a/arch/mips/jazz/jazzdma.c b/arch/mips/jazz/jazzdma.c
index c672c08..f0fd636 100644
--- a/arch/mips/jazz/jazzdma.c
+++ b/arch/mips/jazz/jazzdma.c
@@ -68,8 +68,7 @@ static int __init vdma_init(void)
*/
pgtbl = (VDMA_PGTBL_ENTRY *)__get_free_pages(GFP_KERNEL | GFP_DMA,
get_order(VDMA_PGTBL_SIZE));
- if (!pgtbl)
- BUG();
+ BUG_ON(!pgtbl);
dma_cache_wback_inv((unsigned long)pgtbl, VDMA_PGTBL_SIZE);
pgtbl = (VDMA_PGTBL_ENTRY *)KSEG1ADDR(pgtbl);
diff --git a/arch/mips/kernel/cevt-bcm1480.c b/arch/mips/kernel/cevt-bcm1480.c
index b820661..a5182a2 100644
--- a/arch/mips/kernel/cevt-bcm1480.c
+++ b/arch/mips/kernel/cevt-bcm1480.c
@@ -144,7 +144,6 @@ void __cpuinit sb1480_clockevent_init(void)
action->handler = sibyte_counter_handler;
action->flags = IRQF_DISABLED | IRQF_PERCPU;
- action->mask = cpumask_of_cpu(cpu);
action->name = name;
action->dev_id = cd;
diff --git a/arch/mips/kernel/cevt-sb1250.c b/arch/mips/kernel/cevt-sb1250.c
index a2eebaa..340f53e 100644
--- a/arch/mips/kernel/cevt-sb1250.c
+++ b/arch/mips/kernel/cevt-sb1250.c
@@ -143,7 +143,6 @@ void __cpuinit sb1250_clockevent_init(void)
action->handler = sibyte_counter_handler;
action->flags = IRQF_DISABLED | IRQF_PERCPU;
- action->mask = cpumask_of_cpu(cpu);
action->name = name;
action->dev_id = cd;
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 1bdbcad..b13b8eb 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -183,13 +183,7 @@ void __init check_wait(void)
case CPU_TX49XX:
cpu_wait = r4k_wait_irqoff;
break;
- case CPU_AU1000:
- case CPU_AU1100:
- case CPU_AU1500:
- case CPU_AU1550:
- case CPU_AU1200:
- case CPU_AU1210:
- case CPU_AU1250:
+ case CPU_ALCHEMY:
cpu_wait = au1k_wait;
break;
case CPU_20KC:
@@ -783,37 +777,30 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
switch (c->processor_id & 0xff00) {
case PRID_IMP_AU1_REV1:
case PRID_IMP_AU1_REV2:
+ c->cputype = CPU_ALCHEMY;
switch ((c->processor_id >> 24) & 0xff) {
case 0:
- c->cputype = CPU_AU1000;
__cpu_name[cpu] = "Au1000";
break;
case 1:
- c->cputype = CPU_AU1500;
__cpu_name[cpu] = "Au1500";
break;
case 2:
- c->cputype = CPU_AU1100;
__cpu_name[cpu] = "Au1100";
break;
case 3:
- c->cputype = CPU_AU1550;
__cpu_name[cpu] = "Au1550";
break;
case 4:
- c->cputype = CPU_AU1200;
__cpu_name[cpu] = "Au1200";
- if ((c->processor_id & 0xff) == 2) {
- c->cputype = CPU_AU1250;
+ if ((c->processor_id & 0xff) == 2)
__cpu_name[cpu] = "Au1250";
- }
break;
case 5:
- c->cputype = CPU_AU1210;
__cpu_name[cpu] = "Au1210";
break;
default:
- panic("Unknown Au Core!");
+ __cpu_name[cpu] = "Au1xxx";
break;
}
break;
diff --git a/arch/mips/kernel/i8253.c b/arch/mips/kernel/i8253.c
index f4d1878..689719e 100644
--- a/arch/mips/kernel/i8253.c
+++ b/arch/mips/kernel/i8253.c
@@ -98,7 +98,6 @@ static irqreturn_t timer_interrupt(int irq, void *dev_id)
static struct irqaction irq0 = {
.handler = timer_interrupt,
.flags = IRQF_DISABLED | IRQF_NOBALANCING,
- .mask = CPU_MASK_NONE,
.name = "timer"
};
@@ -121,7 +120,6 @@ void __init setup_pit_timer(void)
cd->min_delta_ns = clockevent_delta2ns(0xF, cd);
clockevents_register_device(cd);
- irq0.mask = cpumask_of_cpu(cpu);
setup_irq(0, &irq0);
}
diff --git a/arch/mips/kernel/i8259.c b/arch/mips/kernel/i8259.c
index 413bd1d..01c0885 100644
--- a/arch/mips/kernel/i8259.c
+++ b/arch/mips/kernel/i8259.c
@@ -306,7 +306,6 @@ static void init_8259A(int auto_eoi)
*/
static struct irqaction irq2 = {
.handler = no_action,
- .mask = CPU_MASK_NONE,
.name = "cascade",
};
diff --git a/arch/mips/kernel/irq-msc01.c b/arch/mips/kernel/irq-msc01.c
index 963c16d..6a8cd28 100644
--- a/arch/mips/kernel/irq-msc01.c
+++ b/arch/mips/kernel/irq-msc01.c
@@ -140,14 +140,16 @@ void __init init_msc_irqs(unsigned long icubase, unsigned int irqbase, msc_irqma
switch (imp->im_type) {
case MSC01_IRQ_EDGE:
- set_irq_chip(irqbase+n, &msc_edgeirq_type);
+ set_irq_chip_and_handler_name(irqbase + n,
+ &msc_edgeirq_type, handle_edge_irq, "edge");
if (cpu_has_veic)
MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);
else
MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl);
break;
case MSC01_IRQ_LEVEL:
- set_irq_chip(irqbase+n, &msc_levelirq_type);
+ set_irq_chip_and_handler_name(irqbase+n,
+ &msc_levelirq_type, handle_level_irq, "level");
if (cpu_has_veic)
MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);
else
diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c
index 0ee2567..55c8a3c 100644
--- a/arch/mips/kernel/irq_cpu.c
+++ b/arch/mips/kernel/irq_cpu.c
@@ -112,7 +112,8 @@ void __init mips_cpu_irq_init(void)
*/
if (cpu_has_mipsmt)
for (i = irq_base; i < irq_base + 2; i++)
- set_irq_chip(i, &mips_mt_cpu_irq_controller);
+ set_irq_chip_and_handler(i, &mips_mt_cpu_irq_controller,
+ handle_percpu_irq);
for (i = irq_base + 2; i < irq_base + 8; i++)
set_irq_chip_and_handler(i, &mips_cpu_irq_controller,
diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c
index 2a47271..6242bc6 100644
--- a/arch/mips/kernel/linux32.c
+++ b/arch/mips/kernel/linux32.c
@@ -133,9 +133,9 @@ SYSCALL_DEFINE4(32_ftruncate64, unsigned long, fd, unsigned long, __dummy,
return sys_ftruncate(fd, merge_64(a2, a3));
}
-SYSCALL_DEFINE5(32_llseek, unsigned long, fd, unsigned long, offset_high,
- unsigned long, offset_low, loff_t __user *, result,
- unsigned long, origin)
+SYSCALL_DEFINE5(32_llseek, unsigned int, fd, unsigned int, offset_high,
+ unsigned int, offset_low, loff_t __user *, result,
+ unsigned int, origin)
{
return sys_llseek(fd, offset_high, offset_low, result, origin);
}
diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
index ca2e402..1eaaa45 100644
--- a/arch/mips/kernel/process.c
+++ b/arch/mips/kernel/process.c
@@ -99,7 +99,7 @@ void flush_thread(void)
{
}
-int copy_thread(int nr, unsigned long clone_flags, unsigned long usp,
+int copy_thread(unsigned long clone_flags, unsigned long usp,
unsigned long unused, struct task_struct *p, struct pt_regs *regs)
{
struct thread_info *ti = task_thread_info(p);
diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S
index 9ab70c3..0b31b9b 100644
--- a/arch/mips/kernel/scall32-o32.S
+++ b/arch/mips/kernel/scall32-o32.S
@@ -650,6 +650,8 @@ einval: li v0, -ENOSYS
sys sys_dup3 3
sys sys_pipe2 2
sys sys_inotify_init1 1
+ sys sys_preadv 6 /* 4330 */
+ sys sys_pwritev 6
.endm
/* We pre-compute the number of _instruction_ bytes needed to
diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S
index 9b46986..c647fd6 100644
--- a/arch/mips/kernel/scall64-64.S
+++ b/arch/mips/kernel/scall64-64.S
@@ -487,4 +487,6 @@ sys_call_table:
PTR sys_dup3
PTR sys_pipe2
PTR sys_inotify_init1
+ PTR sys_preadv
+ PTR sys_pwritev /* 5390 */
.size sys_call_table,.-sys_call_table
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index f61d6b0..c2c16ef 100644
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -413,4 +413,6 @@ EXPORT(sysn32_call_table)
PTR sys_dup3 /* 5290 */
PTR sys_pipe2
PTR sys_inotify_init1
+ PTR sys_preadv
+ PTR sys_pwritev
.size sysn32_call_table,.-sysn32_call_table
diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S
index 60997f1..002fac2 100644
--- a/arch/mips/kernel/scall64-o32.S
+++ b/arch/mips/kernel/scall64-o32.S
@@ -533,4 +533,6 @@ sys_call_table:
PTR sys_dup3
PTR sys_pipe2
PTR sys_inotify_init1
+ PTR compat_sys_preadv /* 4330 */
+ PTR compat_sys_pwritev
.size sys_call_table,.-sys_call_table
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 4430a1f..2950b97 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -277,7 +277,8 @@ static void __init bootmem_init(void)
* not selected. Once that done we can determine the low bound
* of usable memory.
*/
- reserved_end = max(init_initrd(), PFN_UP(__pa_symbol(&_end)));
+ reserved_end = max(init_initrd(),
+ (unsigned long) PFN_UP(__pa_symbol(&_end)));
/*
* max_low_pfn is not a number of pages. The number of pages
diff --git a/arch/mips/kernel/smp-up.c b/arch/mips/kernel/smp-up.c
index ead6c30..878e373 100644
--- a/arch/mips/kernel/smp-up.c
+++ b/arch/mips/kernel/smp-up.c
@@ -13,7 +13,7 @@
/*
* Send inter-processor interrupt
*/
-void up_send_ipi_single(int cpu, unsigned int action)
+static void up_send_ipi_single(int cpu, unsigned int action)
{
panic(KERN_ERR "%s called", __func__);
}
@@ -27,31 +27,31 @@ static inline void up_send_ipi_mask(cpumask_t mask, unsigned int action)
* After we've done initial boot, this function is called to allow the
* board code to clean up state, if needed
*/
-void __cpuinit up_init_secondary(void)
+static void __cpuinit up_init_secondary(void)
{
}
-void __cpuinit up_smp_finish(void)
+static void __cpuinit up_smp_finish(void)
{
}
/* Hook for after all CPUs are online */
-void up_cpus_done(void)
+static void up_cpus_done(void)
{
}
/*
* Firmware CPU startup hook
*/
-void __cpuinit up_boot_secondary(int cpu, struct task_struct *idle)
+static void __cpuinit up_boot_secondary(int cpu, struct task_struct *idle)
{
}
-void __init up_smp_setup(void)
+static void __init up_smp_setup(void)
{
}
-void __init up_prepare_cpus(unsigned int max_cpus)
+static void __init up_prepare_cpus(unsigned int max_cpus)
{
}
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index 3da9470..c937506 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -44,7 +44,7 @@
#include <asm/mipsmtregs.h>
#endif /* CONFIG_MIPS_MT_SMTC */
-volatile cpumask_t cpu_callin_map; /* Bitmask of started secondaries */
+static volatile cpumask_t cpu_callin_map; /* Bitmask of started secondaries */
int __cpu_number_map[NR_CPUS]; /* Map physical to logical */
int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 29fadac..e83da17 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1277,8 +1277,7 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
u32 *w;
unsigned char *b;
- if (!cpu_has_veic && !cpu_has_vint)
- BUG();
+ BUG_ON(!cpu_has_veic && !cpu_has_vint);
if (addr == NULL) {
handler = (unsigned long) do_default_vi;
diff --git a/arch/mips/lasat/interrupt.c b/arch/mips/lasat/interrupt.c
index d1ac7a2..1353fb1 100644
--- a/arch/mips/lasat/interrupt.c
+++ b/arch/mips/lasat/interrupt.c
@@ -104,7 +104,6 @@ asmlinkage void plat_irq_dispatch(void)
static struct irqaction cascade = {
.handler = no_action,
- .mask = CPU_MASK_NONE,
.name = "cascade",
};
diff --git a/arch/mips/lemote/lm2e/irq.c b/arch/mips/lemote/lm2e/irq.c
index 3e0b7be..1d0a09f 100644
--- a/arch/mips/lemote/lm2e/irq.c
+++ b/arch/mips/lemote/lm2e/irq.c
@@ -92,7 +92,6 @@ asmlinkage void plat_irq_dispatch(void)
static struct irqaction cascade_irqaction = {
.handler = no_action,
- .mask = CPU_MASK_NONE,
.name = "cascade",
};
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 871e828..58d9075 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1026,13 +1026,7 @@ static void __cpuinit probe_pcache(void)
c->icache.flags |= MIPS_CACHE_VTAG;
break;
- case CPU_AU1000:
- case CPU_AU1500:
- case CPU_AU1100:
- case CPU_AU1550:
- case CPU_AU1200:
- case CPU_AU1210:
- case CPU_AU1250:
+ case CPU_ALCHEMY:
c->icache.flags |= MIPS_CACHE_IC_F_DC;
break;
}
@@ -1244,7 +1238,7 @@ void au1x00_fixup_config_od(void)
/*
* Au1100 errata actually keeps silence about this bit, so we set it
* just in case for those revisions that require it to be set according
- * to arch/mips/au1000/common/cputable.c
+ * to the (now gone) cpu table.
*/
case 0x02030200: /* Au1100 AB */
case 0x02030201: /* Au1100 BA */
@@ -1314,11 +1308,10 @@ static void __cpuinit coherency_setup(void)
break;
/*
* We need to catch the early Alchemy SOCs with
- * the write-only co_config.od bit and set it back to one...
+ * the write-only co_config.od bit and set it back to one on:
+ * Au1000 rev DA, HA, HB; Au1100 AB, BA, BC, Au1500 AB
*/
- case CPU_AU1000: /* rev. DA, HA, HB */
- case CPU_AU1100: /* rev. AB, BA, BC ?? */
- case CPU_AU1500: /* rev. AB */
+ case CPU_ALCHEMY:
au1x00_fixup_config_od();
break;
diff --git a/arch/mips/mm/highmem.c b/arch/mips/mm/highmem.c
index 8f2cd8e..4481656 100644
--- a/arch/mips/mm/highmem.c
+++ b/arch/mips/mm/highmem.c
@@ -17,8 +17,7 @@ void *__kmap(struct page *page)
void __kunmap(struct page *page)
{
- if (in_interrupt())
- BUG();
+ BUG_ON(in_interrupt());
if (!PageHighMem(page))
return;
kunmap_high(page);
@@ -43,11 +42,11 @@ void *__kmap_atomic(struct page *page, enum km_type type)
if (!PageHighMem(page))
return page_address(page);
+ debug_kmap_atomic(type);
idx = type + KM_TYPE_NR*smp_processor_id();
vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
#ifdef CONFIG_DEBUG_HIGHMEM
- if (!pte_none(*(kmap_pte-idx)))
- BUG();
+ BUG_ON(!pte_none(*(kmap_pte - idx)));
#endif
set_pte(kmap_pte-idx, mk_pte(page, kmap_prot));
local_flush_tlb_one((unsigned long)vaddr);
@@ -66,8 +65,7 @@ void __kunmap_atomic(void *kvaddr, enum km_type type)
return;
}
- if (vaddr != __fix_to_virt(FIX_KMAP_BEGIN+idx))
- BUG();
+ BUG_ON(vaddr != __fix_to_virt(FIX_KMAP_BEGIN + idx));
/*
* force other mappings to Oops if they'll try to access
@@ -91,6 +89,7 @@ void *kmap_atomic_pfn(unsigned long pfn, enum km_type type)
pagefault_disable();
+ debug_kmap_atomic(type);
idx = type + KM_TYPE_NR*smp_processor_id();
vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
set_pte(kmap_pte-idx, pfn_pte(pfn, kmap_prot));
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 137c14b..d934894 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -307,8 +307,7 @@ void __init fixrange_init(unsigned long start, unsigned long end,
if (pmd_none(*pmd)) {
pte = (pte_t *) alloc_bootmem_low_pages(PAGE_SIZE);
set_pmd(pmd, __pmd((unsigned long)pte));
- if (pte != pte_offset_kernel(pmd, 0))
- BUG();
+ BUG_ON(pte != pte_offset_kernel(pmd, 0));
}
vaddr += PMD_SIZE;
}
diff --git a/arch/mips/mm/ioremap.c b/arch/mips/mm/ioremap.c
index 59945b9..0c43248 100644
--- a/arch/mips/mm/ioremap.c
+++ b/arch/mips/mm/ioremap.c
@@ -27,8 +27,7 @@ static inline void remap_area_pte(pte_t * pte, unsigned long address,
end = address + size;
if (end > PMD_SIZE)
end = PMD_SIZE;
- if (address >= end)
- BUG();
+ BUG_ON(address >= end);
pfn = phys_addr >> PAGE_SHIFT;
do {
if (!pte_none(*pte)) {
@@ -52,8 +51,7 @@ static inline int remap_area_pmd(pmd_t * pmd, unsigned long address,
if (end > PGDIR_SIZE)
end = PGDIR_SIZE;
phys_addr -= address;
- if (address >= end)
- BUG();
+ BUG_ON(address >= end);
do {
pte_t * pte = pte_alloc_kernel(pmd, address);
if (!pte)
@@ -75,8 +73,7 @@ static int remap_area_pages(unsigned long address, phys_t phys_addr,
phys_addr -= address;
dir = pgd_offset(&init_mm, address);
flush_cache_all();
- if (address >= end)
- BUG();
+ BUG_ON(address >= end);
do {
pud_t *pud;
pmd_t *pmd;
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index f335cf6..0615b62 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -292,13 +292,6 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
case CPU_R4300:
case CPU_5KC:
case CPU_TX49XX:
- case CPU_AU1000:
- case CPU_AU1100:
- case CPU_AU1500:
- case CPU_AU1550:
- case CPU_AU1200:
- case CPU_AU1210:
- case CPU_AU1250:
case CPU_PR4450:
uasm_i_nop(p);
tlbw(p);
@@ -321,6 +314,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
case CPU_R5500:
if (m4kc_tlbp_war())
uasm_i_nop(p);
+ case CPU_ALCHEMY:
tlbw(p);
break;
diff --git a/arch/mips/mti-malta/malta-init.c b/arch/mips/mti-malta/malta-init.c
index 4832af2..475038a 100644
--- a/arch/mips/mti-malta/malta-init.c
+++ b/arch/mips/mti-malta/malta-init.c
@@ -48,7 +48,7 @@ int *_prom_argv, *_prom_envp;
int init_debug = 0;
-int mips_revision_corid;
+static int mips_revision_corid;
int mips_revision_sconid;
/* Bonito64 system controller register base. */
diff --git a/arch/mips/nxp/pnx833x/common/platform.c b/arch/mips/nxp/pnx833x/common/platform.c
index b1ccbcc..01f8345 100644
--- a/arch/mips/nxp/pnx833x/common/platform.c
+++ b/arch/mips/nxp/pnx833x/common/platform.c
@@ -42,7 +42,7 @@
#include <irq-mapping.h>
#include <pnx833x.h>
-static u64 uart_dmamask = DMA_32BIT_MASK;
+static u64 uart_dmamask = DMA_BIT_MASK(32);
static struct resource pnx833x_uart_resources[] = {
[0] = {
@@ -101,14 +101,14 @@ static struct platform_device pnx833x_uart_device = {
.id = -1,
.dev = {
.dma_mask = &uart_dmamask,
- .coherent_dma_mask = DMA_32BIT_MASK,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = pnx8xxx_ports,
},
.num_resources = ARRAY_SIZE(pnx833x_uart_resources),
.resource = pnx833x_uart_resources,
};
-static u64 ehci_dmamask = DMA_32BIT_MASK;
+static u64 ehci_dmamask = DMA_BIT_MASK(32);
static struct resource pnx833x_usb_ehci_resources[] = {
[0] = {
@@ -128,7 +128,7 @@ static struct platform_device pnx833x_usb_ehci_device = {
.id = -1,
.dev = {
.dma_mask = &ehci_dmamask,
- .coherent_dma_mask = DMA_32BIT_MASK,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
},
.num_resources = ARRAY_SIZE(pnx833x_usb_ehci_resources),
.resource = pnx833x_usb_ehci_resources,
@@ -198,7 +198,7 @@ static struct platform_device pnx833x_i2c1_device = {
};
#endif
-static u64 ethernet_dmamask = DMA_32BIT_MASK;
+static u64 ethernet_dmamask = DMA_BIT_MASK(32);
static struct resource pnx833x_ethernet_resources[] = {
[0] = {
@@ -218,7 +218,7 @@ static struct platform_device pnx833x_ethernet_device = {
.id = -1,
.dev = {
.dma_mask = &ethernet_dmamask,
- .coherent_dma_mask = DMA_32BIT_MASK,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
},
.num_resources = ARRAY_SIZE(pnx833x_ethernet_resources),
.resource = pnx833x_ethernet_resources,
diff --git a/arch/mips/nxp/pnx8550/common/platform.c b/arch/mips/nxp/pnx8550/common/platform.c
index 21d2955..5264cc0 100644
--- a/arch/mips/nxp/pnx8550/common/platform.c
+++ b/arch/mips/nxp/pnx8550/common/platform.c
@@ -92,16 +92,16 @@ struct pnx8xxx_port pnx8xxx_ports[] = {
};
/* The dmamask must be set for OHCI to work */
-static u64 ohci_dmamask = DMA_32BIT_MASK;
+static u64 ohci_dmamask = DMA_BIT_MASK(32);
-static u64 uart_dmamask = DMA_32BIT_MASK;
+static u64 uart_dmamask = DMA_BIT_MASK(32);
static struct platform_device pnx8550_usb_ohci_device = {
.name = "pnx8550-ohci",
.id = -1,
.dev = {
.dma_mask = &ohci_dmamask,
- .coherent_dma_mask = DMA_32BIT_MASK,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
},
.num_resources = ARRAY_SIZE(pnx8550_usb_ohci_resources),
.resource = pnx8550_usb_ohci_resources,
@@ -112,7 +112,7 @@ static struct platform_device pnx8550_uart_device = {
.id = -1,
.dev = {
.dma_mask = &uart_dmamask,
- .coherent_dma_mask = DMA_32BIT_MASK,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = pnx8xxx_ports,
},
.num_resources = ARRAY_SIZE(pnx8550_uart_resources),
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_usb.c b/arch/mips/pmc-sierra/msp71xx/msp_usb.c
index f7ca4f5..0ee01e3 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_usb.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_usb.c
@@ -49,14 +49,14 @@ static struct resource msp_usbhost_resources [] = {
},
};
-static u64 msp_usbhost_dma_mask = DMA_32BIT_MASK;
+static u64 msp_usbhost_dma_mask = DMA_BIT_MASK(32);
static struct platform_device msp_usbhost_device = {
.name = "pmcmsp-ehci",
.id = 0,
.dev = {
.dma_mask = &msp_usbhost_dma_mask,
- .coherent_dma_mask = DMA_32BIT_MASK,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
},
.num_resources = ARRAY_SIZE(msp_usbhost_resources),
.resource = msp_usbhost_resources,
@@ -77,14 +77,14 @@ static struct resource msp_usbdev_resources [] = {
},
};
-static u64 msp_usbdev_dma_mask = DMA_32BIT_MASK;
+static u64 msp_usbdev_dma_mask = DMA_BIT_MASK(32);
static struct platform_device msp_usbdev_device = {
.name = "msp71xx_udc",
.id = 0,
.dev = {
.dma_mask = &msp_usbdev_dma_mask,
- .coherent_dma_mask = DMA_32BIT_MASK,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
},
.num_resources = ARRAY_SIZE(msp_usbdev_resources),
.resource = msp_usbdev_resources,
diff --git a/arch/mips/sgi-ip27/ip27-berr.c b/arch/mips/sgi-ip27/ip27-berr.c
index 7d05e68..04cebad 100644
--- a/arch/mips/sgi-ip27/ip27-berr.c
+++ b/arch/mips/sgi-ip27/ip27-berr.c
@@ -66,7 +66,7 @@ int ip27_be_handler(struct pt_regs *regs, int is_fixup)
printk("Slice %c got %cbe at 0x%lx\n", 'A' + cpu, data ? 'd' : 'i',
regs->cp0_epc);
printk("Hub information:\n");
- printk("ERR_INT_PEND = 0x%06lx\n", LOCAL_HUB_L(PI_ERR_INT_PEND));
+ printk("ERR_INT_PEND = 0x%06llx\n", LOCAL_HUB_L(PI_ERR_INT_PEND));
errst0 = LOCAL_HUB_L(cpu ? PI_ERR_STATUS0_B : PI_ERR_STATUS0_A);
errst1 = LOCAL_HUB_L(cpu ? PI_ERR_STATUS1_B : PI_ERR_STATUS1_A);
dump_hub_information(errst0, errst1);
diff --git a/arch/mips/sgi-ip27/ip27-nmi.c b/arch/mips/sgi-ip27/ip27-nmi.c
index 64459e7..6c5a630 100644
--- a/arch/mips/sgi-ip27/ip27-nmi.c
+++ b/arch/mips/sgi-ip27/ip27-nmi.c
@@ -143,8 +143,8 @@ void nmi_dump_hub_irq(nasid_t nasid, int slice)
pend0 = REMOTE_HUB_L(nasid, PI_INT_PEND0);
pend1 = REMOTE_HUB_L(nasid, PI_INT_PEND1);
- printk("PI_INT_MASK0: %16lx PI_INT_MASK1: %16lx\n", mask0, mask1);
- printk("PI_INT_PEND0: %16lx PI_INT_PEND1: %16lx\n", pend0, pend1);
+ printk("PI_INT_MASK0: %16Lx PI_INT_MASK1: %16Lx\n", mask0, mask1);
+ printk("PI_INT_PEND0: %16Lx PI_INT_PEND1: %16Lx\n", pend0, pend1);
printk("\n\n");
}
@@ -219,7 +219,7 @@ cont_nmi_dump(void)
if (i == 1000) {
for_each_online_node(node)
if (NODEPDA(node)->dump_count == 0) {
- cpu = node_to_first_cpu(node);
+ cpu = cpumask_first(cpumask_of_node(node));
for (n=0; n < CNODE_NUM_CPUS(node); cpu++, n++) {
CPUMASK_SETB(nmied_cpus, cpu);
/*
diff --git a/arch/mips/sgi-ip27/ip27-smp.c b/arch/mips/sgi-ip27/ip27-smp.c
index 5b47d6b..cbcd7eb 100644
--- a/arch/mips/sgi-ip27/ip27-smp.c
+++ b/arch/mips/sgi-ip27/ip27-smp.c
@@ -221,7 +221,7 @@ static void __init ip27_smp_setup(void)
* Assumption to be fixed: we're always booted on logical / physical
* processor 0. While we're always running on logical processor 0
* this still means this is physical processor zero; it might for
- * example be disabled in the firwware.
+ * example be disabled in the firmware.
*/
alloc_cpupda(0, 0);
}
diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c
index 0d6b666..83a0b3c 100644
--- a/arch/mips/sgi-ip32/ip32-irq.c
+++ b/arch/mips/sgi-ip32/ip32-irq.c
@@ -115,14 +115,12 @@ extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id);
struct irqaction memerr_irq = {
.handler = crime_memerr_intr,
.flags = IRQF_DISABLED,
- .mask = CPU_MASK_NONE,
.name = "CRIME memory error",
};
struct irqaction cpuerr_irq = {
.handler = crime_cpuerr_intr,
.flags = IRQF_DISABLED,
- .mask = CPU_MASK_NONE,
.name = "CRIME CPU error",
};
@@ -325,16 +323,11 @@ static void mask_and_ack_maceisa_irq(unsigned int irq)
{
unsigned long mace_int;
- switch (irq) {
- case MACEISA_PARALLEL_IRQ:
- case MACEISA_SERIAL1_TDMAPR_IRQ:
- case MACEISA_SERIAL2_TDMAPR_IRQ:
- /* edge triggered */
- mace_int = mace->perif.ctrl.istat;
- mace_int &= ~(1 << (irq - MACEISA_AUDIO_SW_IRQ));
- mace->perif.ctrl.istat = mace_int;
- break;
- }
+ /* edge triggered */
+ mace_int = mace->perif.ctrl.istat;
+ mace_int &= ~(1 << (irq - MACEISA_AUDIO_SW_IRQ));
+ mace->perif.ctrl.istat = mace_int;
+
disable_maceisa_irq(irq);
}
@@ -344,7 +337,16 @@ static void end_maceisa_irq(unsigned irq)
enable_maceisa_irq(irq);
}
-static struct irq_chip ip32_maceisa_interrupt = {
+static struct irq_chip ip32_maceisa_level_interrupt = {
+ .name = "IP32 MACE ISA",
+ .ack = disable_maceisa_irq,
+ .mask = disable_maceisa_irq,
+ .mask_ack = disable_maceisa_irq,
+ .unmask = enable_maceisa_irq,
+ .end = end_maceisa_irq,
+};
+
+static struct irq_chip ip32_maceisa_edge_interrupt = {
.name = "IP32 MACE ISA",
.ack = mask_and_ack_maceisa_irq,
.mask = disable_maceisa_irq,
@@ -500,27 +502,50 @@ void __init arch_init_irq(void)
for (irq = CRIME_IRQ_BASE; irq <= IP32_IRQ_MAX; irq++) {
switch (irq) {
case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ:
- set_irq_chip(irq, &ip32_mace_interrupt);
+ set_irq_chip_and_handler_name(irq,&ip32_mace_interrupt,
+ handle_level_irq, "level");
break;
+
case MACEPCI_SCSI0_IRQ ... MACEPCI_SHARED2_IRQ:
- set_irq_chip(irq, &ip32_macepci_interrupt);
+ set_irq_chip_and_handler_name(irq,
+ &ip32_macepci_interrupt, handle_level_irq,
+ "level");
break;
+
case CRIME_GBE0_IRQ ... CRIME_GBE3_IRQ:
- set_irq_chip(irq, &crime_edge_interrupt);
+ set_irq_chip_and_handler_name(irq,
+ &crime_edge_interrupt, handle_edge_irq, "edge");
break;
case CRIME_CPUERR_IRQ:
case CRIME_MEMERR_IRQ:
- set_irq_chip(irq, &crime_level_interrupt);
+ set_irq_chip_and_handler_name(irq,
+ &crime_level_interrupt, handle_level_irq,
+ "level");
break;
+
case CRIME_RE_EMPTY_E_IRQ ... CRIME_RE_IDLE_E_IRQ:
case CRIME_SOFT0_IRQ ... CRIME_SOFT2_IRQ:
- set_irq_chip(irq, &crime_edge_interrupt);
+ set_irq_chip_and_handler_name(irq,
+ &crime_edge_interrupt, handle_edge_irq, "edge");
break;
+
case CRIME_VICE_IRQ:
- set_irq_chip(irq, &crime_edge_interrupt);
+ set_irq_chip_and_handler_name(irq,
+ &crime_edge_interrupt, handle_edge_irq, "edge");
+ break;
+
+ case MACEISA_PARALLEL_IRQ:
+ case MACEISA_SERIAL1_TDMAPR_IRQ:
+ case MACEISA_SERIAL2_TDMAPR_IRQ:
+ set_irq_chip_and_handler_name(irq,
+ &ip32_maceisa_edge_interrupt, handle_edge_irq,
+ "edge");
break;
+
default:
- set_irq_chip(irq, &ip32_maceisa_interrupt);
+ set_irq_chip_and_handler_name(irq,
+ &ip32_maceisa_level_interrupt, handle_level_irq,
+ "level");
break;
}
}
diff --git a/arch/mips/sgi-ip32/ip32-memory.c b/arch/mips/sgi-ip32/ip32-memory.c
index ca93ecf..828ce13 100644
--- a/arch/mips/sgi-ip32/ip32-memory.c
+++ b/arch/mips/sgi-ip32/ip32-memory.c
@@ -36,7 +36,7 @@ void __init prom_meminit(void)
if (base + size > (256 << 20))
base += CRIME_HI_MEM_BASE;
- printk("CRIME MC: bank %u base 0x%016lx size %luMiB\n",
+ printk("CRIME MC: bank %u base 0x%016Lx size %LuMiB\n",
bank, base, size >> 20);
add_memory_region(base, size, BOOT_MEM_RAM);
}
diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c
index 12b465d..352352b 100644
--- a/arch/mips/sibyte/bcm1480/irq.c
+++ b/arch/mips/sibyte/bcm1480/irq.c
@@ -236,7 +236,7 @@ void __init init_bcm1480_irqs(void)
int i;
for (i = 0; i < BCM1480_NR_IRQS; i++) {
- set_irq_chip(i, &bcm1480_irq_type);
+ set_irq_chip_and_handler(i, &bcm1480_irq_type, handle_level_irq);
bcm1480_irq_owner[i] = 0;
}
}
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index 808ac29..c08ff58 100644
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -220,7 +220,7 @@ void __init init_sb1250_irqs(void)
int i;
for (i = 0; i < SB1250_NR_IRQS; i++) {
- set_irq_chip(i, &sb1250_irq_type);
+ set_irq_chip_and_handler(i, &sb1250_irq_type, handle_level_irq);
sb1250_irq_owner[i] = 0;
}
}
diff --git a/arch/mips/sni/a20r.c b/arch/mips/sni/a20r.c
index 3f8cf5e..7dd76fb 100644
--- a/arch/mips/sni/a20r.c
+++ b/arch/mips/sni/a20r.c
@@ -219,7 +219,7 @@ void __init sni_a20r_irq_init(void)
int i;
for (i = SNI_A20R_IRQ_BASE + 2 ; i < SNI_A20R_IRQ_BASE + 8; i++)
- set_irq_chip(i, &a20r_irq_type);
+ set_irq_chip_and_handler(i, &a20r_irq_type, handle_level_irq);
sni_hwint = a20r_hwint;
change_c0_status(ST0_IM, IE_IRQ0);
setup_irq(SNI_A20R_IRQ_BASE + 3, &sni_isa_irq);
diff --git a/arch/mips/sni/pcimt.c b/arch/mips/sni/pcimt.c
index 834650f..74e6c67 100644
--- a/arch/mips/sni/pcimt.c
+++ b/arch/mips/sni/pcimt.c
@@ -304,7 +304,7 @@ void __init sni_pcimt_irq_init(void)
mips_cpu_irq_init();
/* Actually we've got more interrupts to handle ... */
for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_SCSI; i++)
- set_irq_chip(i, &pcimt_irq_type);
+ set_irq_chip_and_handler(i, &pcimt_irq_type, handle_level_irq);
sni_hwint = sni_pcimt_hwint;
change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ3);
}
diff --git a/arch/mips/sni/pcit.c b/arch/mips/sni/pcit.c
index e5f12cf..071a957 100644
--- a/arch/mips/sni/pcit.c
+++ b/arch/mips/sni/pcit.c
@@ -246,7 +246,7 @@ void __init sni_pcit_irq_init(void)
mips_cpu_irq_init();
for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++)
- set_irq_chip(i, &pcit_irq_type);
+ set_irq_chip_and_handler(i, &pcit_irq_type, handle_level_irq);
*(volatile u32 *)SNI_PCIT_INT_REG = 0;
sni_hwint = sni_pcit_hwint;
change_c0_status(ST0_IM, IE_IRQ1);
@@ -259,7 +259,7 @@ void __init sni_pcit_cplus_irq_init(void)
mips_cpu_irq_init();
for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++)
- set_irq_chip(i, &pcit_irq_type);
+ set_irq_chip_and_handler(i, &pcit_irq_type, handle_level_irq);
*(volatile u32 *)SNI_PCIT_INT_REG = 0x40000000;
sni_hwint = sni_pcit_hwint_cplus;
change_c0_status(ST0_IM, IE_IRQ0);
diff --git a/arch/mips/sni/rm200.c b/arch/mips/sni/rm200.c
index 5310aa7..5e68781 100644
--- a/arch/mips/sni/rm200.c
+++ b/arch/mips/sni/rm200.c
@@ -359,7 +359,8 @@ void sni_rm200_init_8259A(void)
* IRQ2 is cascade interrupt to second interrupt controller
*/
static struct irqaction sni_rm200_irq2 = {
- no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL
+ .handler = no_action,
+ .name = "cascade",
};
static struct resource sni_rm200_pic1_resource = {
@@ -487,7 +488,7 @@ void __init sni_rm200_irq_init(void)
mips_cpu_irq_init();
/* Actually we've got more interrupts to handle ... */
for (i = SNI_RM200_INT_START; i <= SNI_RM200_INT_END; i++)
- set_irq_chip(i, &rm200_irq_type);
+ set_irq_chip_and_handler(i, &rm200_irq_type, handle_level_irq);
sni_hwint = sni_rm200_hwint;
change_c0_status(ST0_IM, IE_IRQ0);
setup_irq(SNI_RM200_INT_START + 0, &sni_rm200_i8259A_irq);
diff --git a/arch/mips/txx9/Kconfig b/arch/mips/txx9/Kconfig
index 226e8bb..0db7cf3 100644
--- a/arch/mips/txx9/Kconfig
+++ b/arch/mips/txx9/Kconfig
@@ -20,7 +20,6 @@ config MACH_TXX9
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_BIG_ENDIAN
- select GENERIC_HARDIRQS_NO__DO_IRQ
config TOSHIBA_JMR3927
bool "Toshiba JMR-TX3927 board"
diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c
index a13a08b..8a266c6 100644
--- a/arch/mips/txx9/generic/setup.c
+++ b/arch/mips/txx9/generic/setup.c
@@ -32,6 +32,7 @@
#include <asm/txx9/generic.h>
#include <asm/txx9/pci.h>
#include <asm/txx9tmr.h>
+#include <asm/txx9/ndfmc.h>
#ifdef CONFIG_CPU_TX49XX
#include <asm/txx9/tx4938.h>
#endif
@@ -691,6 +692,26 @@ void __init txx9_physmap_flash_init(int no, unsigned long addr,
#endif
}
+void __init txx9_ndfmc_init(unsigned long baseaddr,
+ const struct txx9ndfmc_platform_data *pdata)
+{
+#if defined(CONFIG_MTD_NAND_TXX9NDFMC) || \
+ defined(CONFIG_MTD_NAND_TXX9NDFMC_MODULE)
+ struct resource res = {
+ .start = baseaddr,
+ .end = baseaddr + 0x1000 - 1,
+ .flags = IORESOURCE_MEM,
+ };
+ struct platform_device *pdev = platform_device_alloc("txx9ndfmc", -1);
+
+ if (!pdev ||
+ platform_device_add_resources(pdev, &res, 1) ||
+ platform_device_add_data(pdev, pdata, sizeof(*pdata)) ||
+ platform_device_add(pdev))
+ platform_device_put(pdev);
+#endif
+}
+
#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
static DEFINE_SPINLOCK(txx9_iocled_lock);
diff --git a/arch/mips/txx9/generic/setup_tx4938.c b/arch/mips/txx9/generic/setup_tx4938.c
index 25819ff..f0844f8 100644
--- a/arch/mips/txx9/generic/setup_tx4938.c
+++ b/arch/mips/txx9/generic/setup_tx4938.c
@@ -23,6 +23,7 @@
#include <asm/txx9tmr.h>
#include <asm/txx9pio.h>
#include <asm/txx9/generic.h>
+#include <asm/txx9/ndfmc.h>
#include <asm/txx9/tx4938.h>
static void __init tx4938_wdr_init(void)
@@ -382,6 +383,26 @@ void __init tx4938_ata_init(unsigned int irq, unsigned int shift, int tune)
platform_device_put(pdev);
}
+void __init tx4938_ndfmc_init(unsigned int hold, unsigned int spw)
+{
+ struct txx9ndfmc_platform_data plat_data = {
+ .shift = 1,
+ .gbus_clock = txx9_gbus_clock,
+ .hold = hold,
+ .spw = spw,
+ .ch_mask = 1,
+ };
+ unsigned long baseaddr = TX4938_NDFMC_REG & 0xfffffffffULL;
+
+#ifdef __BIG_ENDIAN
+ baseaddr += 4;
+#endif
+ if ((__raw_readq(&tx4938_ccfgptr->pcfg) &
+ (TX4938_PCFG_ATA_SEL|TX4938_PCFG_ISA_SEL|TX4938_PCFG_NDF_SEL)) ==
+ TX4938_PCFG_NDF_SEL)
+ txx9_ndfmc_init(baseaddr, &plat_data);
+}
+
static void __init tx4938_stop_unused_modules(void)
{
__u64 pcfg, rst = 0, ckd = 0;
diff --git a/arch/mips/txx9/generic/setup_tx4939.c b/arch/mips/txx9/generic/setup_tx4939.c
index 5544096..7a25b57 100644
--- a/arch/mips/txx9/generic/setup_tx4939.c
+++ b/arch/mips/txx9/generic/setup_tx4939.c
@@ -27,6 +27,7 @@
#include <asm/txx9irq.h>
#include <asm/txx9tmr.h>
#include <asm/txx9/generic.h>
+#include <asm/txx9/ndfmc.h>
#include <asm/txx9/tx4939.h>
static void __init tx4939_wdr_init(void)
@@ -457,6 +458,22 @@ void __init tx4939_rtc_init(void)
platform_device_register(&rtc_dev);
}
+void __init tx4939_ndfmc_init(unsigned int hold, unsigned int spw,
+ unsigned char ch_mask, unsigned char wide_mask)
+{
+ struct txx9ndfmc_platform_data plat_data = {
+ .shift = 1,
+ .gbus_clock = txx9_gbus_clock,
+ .hold = hold,
+ .spw = spw,
+ .flags = NDFMC_PLAT_FLAG_NO_RSTR | NDFMC_PLAT_FLAG_HOLDADD |
+ NDFMC_PLAT_FLAG_DUMMYWRITE,
+ .ch_mask = ch_mask,
+ .wide_mask = wide_mask,
+ };
+ txx9_ndfmc_init(TX4939_NDFMC_REG & 0xfffffffffULL, &plat_data);
+}
+
static void __init tx4939_stop_unused_modules(void)
{
__u64 pcfg, rst = 0, ckd = 0;
diff --git a/arch/mips/txx9/rbtx4938/setup.c b/arch/mips/txx9/rbtx4938/setup.c
index 547ff29..65d13df 100644
--- a/arch/mips/txx9/rbtx4938/setup.c
+++ b/arch/mips/txx9/rbtx4938/setup.c
@@ -352,6 +352,8 @@ static void __init rbtx4938_device_init(void)
rbtx4938_ne_init();
tx4938_wdt_init();
rbtx4938_mtd_init();
+ /* TC58DVM82A1FT: tDH=10ns, tWP=tRP=tREADID=35ns */
+ tx4938_ndfmc_init(10, 35);
tx4938_ata_init(RBTX4938_IRQ_IOC_ATA, 0, 1);
txx9_iocled_init(RBTX4938_LED_ADDR - IO_BASE, -1, 8, 1, "green", NULL);
}
diff --git a/arch/mips/txx9/rbtx4939/setup.c b/arch/mips/txx9/rbtx4939/setup.c
index 656603b..011e1e3 100644
--- a/arch/mips/txx9/rbtx4939/setup.c
+++ b/arch/mips/txx9/rbtx4939/setup.c
@@ -16,6 +16,9 @@
#include <linux/leds.h>
#include <linux/interrupt.h>
#include <linux/smc91x.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/map.h>
#include <asm/reboot.h>
#include <asm/txx9/generic.h>
#include <asm/txx9/pci.h>
@@ -282,6 +285,159 @@ static void rbtx4939_7segled_putc(unsigned int pos, unsigned char val)
__rbtx4939_7segled_putc(pos, val);
}
+#if defined(CONFIG_MTD_RBTX4939) || defined(CONFIG_MTD_RBTX4939_MODULE)
+/* special mapping for boot rom */
+static unsigned long rbtx4939_flash_fixup_ofs(unsigned long ofs)
+{
+ u8 bdipsw = readb(rbtx4939_bdipsw_addr) & 0x0f;
+ unsigned char shift;
+
+ if (bdipsw & 8) {
+ /* BOOT Mode: USER ROM1 / USER ROM2 */
+ shift = bdipsw & 3;
+ /* rotate A[23:22] */
+ return (ofs & ~0xc00000) | ((((ofs >> 22) + shift) & 3) << 22);
+ }
+#ifdef __BIG_ENDIAN
+ if (bdipsw == 0)
+ /* BOOT Mode: Monitor ROM */
+ ofs ^= 0x400000; /* swap A[22] */
+#endif
+ return ofs;
+}
+
+static map_word rbtx4939_flash_read16(struct map_info *map, unsigned long ofs)
+{
+ map_word r;
+
+ ofs = rbtx4939_flash_fixup_ofs(ofs);
+ r.x[0] = __raw_readw(map->virt + ofs);
+ return r;
+}
+
+static void rbtx4939_flash_write16(struct map_info *map, const map_word datum,
+ unsigned long ofs)
+{
+ ofs = rbtx4939_flash_fixup_ofs(ofs);
+ __raw_writew(datum.x[0], map->virt + ofs);
+ mb(); /* see inline_map_write() in mtd/map.h */
+}
+
+static void rbtx4939_flash_copy_from(struct map_info *map, void *to,
+ unsigned long from, ssize_t len)
+{
+ u8 bdipsw = readb(rbtx4939_bdipsw_addr) & 0x0f;
+ unsigned char shift;
+ ssize_t curlen;
+
+ from += (unsigned long)map->virt;
+ if (bdipsw & 8) {
+ /* BOOT Mode: USER ROM1 / USER ROM2 */
+ shift = bdipsw & 3;
+ while (len) {
+ curlen = min_t(unsigned long, len,
+ 0x400000 - (from & (0x400000 - 1)));
+ memcpy(to,
+ (void *)((from & ~0xc00000) |
+ ((((from >> 22) + shift) & 3) << 22)),
+ curlen);
+ len -= curlen;
+ from += curlen;
+ to += curlen;
+ }
+ return;
+ }
+#ifdef __BIG_ENDIAN
+ if (bdipsw == 0) {
+ /* BOOT Mode: Monitor ROM */
+ while (len) {
+ curlen = min_t(unsigned long, len,
+ 0x400000 - (from & (0x400000 - 1)));
+ memcpy(to, (void *)(from ^ 0x400000), curlen);
+ len -= curlen;
+ from += curlen;
+ to += curlen;
+ }
+ return;
+ }
+#endif
+ memcpy(to, (void *)from, len);
+}
+
+static void rbtx4939_flash_map_init(struct map_info *map)
+{
+ map->read = rbtx4939_flash_read16;
+ map->write = rbtx4939_flash_write16;
+ map->copy_from = rbtx4939_flash_copy_from;
+}
+
+static void __init rbtx4939_mtd_init(void)
+{
+ static struct {
+ struct platform_device dev;
+ struct resource res;
+ struct rbtx4939_flash_data data;
+ } pdevs[4];
+ int i;
+ static char names[4][8];
+ static struct mtd_partition parts[4];
+ struct rbtx4939_flash_data *boot_pdata = &pdevs[0].data;
+ u8 bdipsw = readb(rbtx4939_bdipsw_addr) & 0x0f;
+
+ if (bdipsw & 8) {
+ /* BOOT Mode: USER ROM1 / USER ROM2 */
+ boot_pdata->nr_parts = 4;
+ for (i = 0; i < boot_pdata->nr_parts; i++) {
+ sprintf(names[i], "img%d", 4 - i);
+ parts[i].name = names[i];
+ parts[i].size = 0x400000;
+ parts[i].offset = MTDPART_OFS_NXTBLK;
+ }
+ } else if (bdipsw == 0) {
+ /* BOOT Mode: Monitor ROM */
+ boot_pdata->nr_parts = 2;
+ strcpy(names[0], "big");
+ strcpy(names[1], "little");
+ for (i = 0; i < boot_pdata->nr_parts; i++) {
+ parts[i].name = names[i];
+ parts[i].size = 0x400000;
+ parts[i].offset = MTDPART_OFS_NXTBLK;
+ }
+ } else {
+ /* BOOT Mode: ROM Emulator */
+ boot_pdata->nr_parts = 2;
+ parts[0].name = "boot";
+ parts[0].offset = 0xc00000;
+ parts[0].size = 0x400000;
+ parts[1].name = "user";
+ parts[1].offset = 0;
+ parts[1].size = 0xc00000;
+ }
+ boot_pdata->parts = parts;
+ boot_pdata->map_init = rbtx4939_flash_map_init;
+
+ for (i = 0; i < ARRAY_SIZE(pdevs); i++) {
+ struct resource *r = &pdevs[i].res;
+ struct platform_device *dev = &pdevs[i].dev;
+
+ r->start = 0x1f000000 - i * 0x1000000;
+ r->end = r->start + 0x1000000 - 1;
+ r->flags = IORESOURCE_MEM;
+ pdevs[i].data.width = 2;
+ dev->num_resources = 1;
+ dev->resource = r;
+ dev->id = i;
+ dev->name = "rbtx4939-flash";
+ dev->dev.platform_data = &pdevs[i].data;
+ platform_device_register(dev);
+ }
+}
+#else
+static void __init rbtx4939_mtd_init(void)
+{
+}
+#endif
+
static void __init rbtx4939_arch_init(void)
{
rbtx4939_pci_setup();
@@ -333,6 +489,11 @@ static void __init rbtx4939_device_init(void)
platform_device_add_data(pdev, &smc_pdata, sizeof(smc_pdata)) ||
platform_device_add(pdev))
platform_device_put(pdev);
+ rbtx4939_mtd_init();
+ /* TC58DVM82A1FT: tDH=10ns, tWP=tRP=tREADID=35ns */
+ tx4939_ndfmc_init(10, 35,
+ (1 << 1) | (1 << 2),
+ (1 << 2)); /* ch1:8bit, ch2:16bit */
rbtx4939_led_setup();
tx4939_wdt_init();
tx4939_ata_init();
diff --git a/arch/mips/vr41xx/common/irq.c b/arch/mips/vr41xx/common/irq.c
index 92dd1a0..9cc3891 100644
--- a/arch/mips/vr41xx/common/irq.c
+++ b/arch/mips/vr41xx/common/irq.c
@@ -32,7 +32,6 @@ static irq_cascade_t irq_cascade[NR_IRQS] __cacheline_aligned;
static struct irqaction cascade_irqaction = {
.handler = no_action,
- .mask = CPU_MASK_NONE,
.name = "cascade",
};