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author | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2008-06-27 21:52:26 (GMT) |
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committer | Ralf Baechle <ralf@linux-mips.org> | 2008-07-03 18:14:27 (GMT) |
commit | 7e3297dc280f88ec0c6619a895f3d449776f952e (patch) | |
tree | b67495185c12a6477de506a44ebaf169de4f1f46 /arch/mips | |
parent | 1faf7f25b2aa4fcd2ae0ec2fd2e9fb9ff4bfee10 (diff) | |
download | linux-fsl-qoriq-7e3297dc280f88ec0c6619a895f3d449776f952e.tar.xz |
[MIPS] IP22: Fix crashes due to wrong L1_CACHE_BYTES
The introduction of a real dma cache invalidate makes it important
to have a correct cache line size, otherwise the kernel will gives
out two memory segment, which might share one cache line. The R4400
Indy/Indigo2 CPU modules are using a second level cache line size
of 128 bytes, so MIPS_L1_CACHE_SHIFT needs to be bumped up to 7 for
IP22.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r-- | arch/mips/Kconfig | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index e5a7c5d..24c5dee 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1006,7 +1006,7 @@ config BOOT_ELF32 config MIPS_L1_CACHE_SHIFT int default "4" if MACH_DECSTATION - default "7" if SGI_IP27 || SGI_IP28 || SNI_RM + default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM default "4" if PMC_MSP4200_EVAL default "5" |