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authorAnton Blanchard <anton@samba.org>2009-10-27 18:31:29 (GMT)
committerPaul Mackerras <paulus@samba.org>2009-10-28 05:13:02 (GMT)
commit81cd5ae303e88a1e9d3a3e0f1fe8abd100edde16 (patch)
treecebb1b316c4f2eddd99f4caad5460e9abf8ee1c4 /arch/powerpc/include/asm/reg.h
parentbc284e5d9d6da48934a177db92bf8e09b96a9cb8 (diff)
downloadlinux-fsl-qoriq-81cd5ae303e88a1e9d3a3e0f1fe8abd100edde16.tar.xz
powerpc: perf_event: Enable SDAR in continous sample mode
In continuous sampling mode we want the SDAR to update. While we can select between dcache misses and ERAT (L1-TLB) misses, a decent default is to enable both. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/powerpc/include/asm/reg.h')
-rw-r--r--arch/powerpc/include/asm/reg.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 6315edc..bc8dd53 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -489,6 +489,8 @@
#define SPRN_MMCR1 798
#define SPRN_MMCRA 0x312
#define MMCRA_SDSYNC 0x80000000UL /* SDAR synced with SIAR */
+#define MMCRA_SDAR_DCACHE_MISS 0x40000000UL
+#define MMCRA_SDAR_ERAT_MISS 0x20000000UL
#define MMCRA_SIHV 0x10000000UL /* state of MSR HV when SIAR set */
#define MMCRA_SIPR 0x08000000UL /* state of MSR PR when SIAR set */
#define MMCRA_SLOT 0x07000000UL /* SLOT bits (37-39) */