diff options
| author | Chenhui Zhao <chenhui.zhao@freescale.com> | 2014-01-22 08:41:58 (GMT) |
|---|---|---|
| committer | Jose Rivera <German.Rivera@freescale.com> | 2014-04-05 21:56:31 (GMT) |
| commit | 2c13e1422184161e05610562c9f8313feb9bed0f (patch) | |
| tree | abddecec66221a3053bf20ea72e5fc11e3713896 /arch/powerpc/include | |
| parent | dc7fa525149498cc205690d88c61ec13fe1da69f (diff) | |
| download | linux-fsl-qoriq-2c13e1422184161e05610562c9f8313feb9bed0f.tar.xz | |
powerpc/pm: support deep sleep feature on T104x
T104x has deep sleep feature, which can switch off most parts of
the SoC when it is in deep sleep mode. This way, it becomes more
energy-efficient.
The DDR controller will also be powered off in deep sleep. Therefore,
the last stage (the latter part of fsl_dp_enter_low) will run without DDR
access. This piece of code and related TLBs are prefetched in advance.
Due to the different initialization code between 32-bit and 64-bit, they
have seperate resume entry and precedure.
The feature supports 32-bit and 64-bit kernel mode.
Change-Id: I9b9b9188fdc67167030658b6cc1d0a1cbe7e2180
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/10709
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Yang Li <LeoLi@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
Diffstat (limited to 'arch/powerpc/include')
| -rw-r--r-- | arch/powerpc/include/asm/fsl_pm.h | 19 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/reg_booke.h | 1 |
2 files changed, 20 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/fsl_pm.h b/arch/powerpc/include/asm/fsl_pm.h index 03f35a4..d06adaa 100644 --- a/arch/powerpc/include/asm/fsl_pm.h +++ b/arch/powerpc/include/asm/fsl_pm.h @@ -12,6 +12,7 @@ #define __PPC_FSL_PM_H #ifdef __KERNEL__ +#ifndef __ASSEMBLY__ #define E500_PM_PH10 1 #define E500_PM_PH15 2 #define E500_PM_PH20 3 @@ -33,5 +34,23 @@ struct fsl_pm_ops { }; extern const struct fsl_pm_ops *qoriq_pm_ops; + +struct fsm_reg_vals; + +extern void fsl_dp_fsm_setup(void __iomem *dcsr_base, struct fsm_reg_vals *val); +extern void fsl_dp_fsm_clean(void __iomem *dcsr_base, struct fsm_reg_vals *val); + +extern int fsl_dp_iomap(void); +extern void fsl_dp_iounmap(void); + +extern int fsl_enter_epu_deepsleep(void); +extern void fsl_dp_enter_low(void __iomem *ccsr_base, void __iomem *dcsr_base, + void __iomem *pld_base, int pld_flag); +extern void fsl_booke_deep_sleep_resume(void); +#endif /* __ASSEMBLY__ */ + +#define T1040QDS_TETRA_FLAG 1 +#define T104xRDB_CPLD_FLAG 2 + #endif /* __KERNEL__ */ #endif /* __PPC_FSL_PM_H */ diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h index 1353383..56d1f27 100644 --- a/arch/powerpc/include/asm/reg_booke.h +++ b/arch/powerpc/include/asm/reg_booke.h @@ -110,6 +110,7 @@ #define SPRN_IVOR39 0x1B1 /* Interrupt Vector Offset Register 39 */ #define SPRN_IVOR40 0x1B2 /* Interrupt Vector Offset Register 40 */ #define SPRN_IVOR41 0x1B3 /* Interrupt Vector Offset Register 41 */ +#define SPRN_IVOR42 0x1B4 /* Interrupt Vector Offset Register 42 */ #define SPRN_GIVOR2 0x1B8 /* Guest IVOR2 */ #define SPRN_GIVOR3 0x1B9 /* Guest IVOR3 */ #define SPRN_GIVOR4 0x1BA /* Guest IVOR4 */ |