diff options
| author | Mihai Caraman <mihai.caraman@freescale.com> | 2014-04-25 19:56:11 (GMT) |
|---|---|---|
| committer | Jose Rivera <German.Rivera@freescale.com> | 2014-04-30 02:05:10 (GMT) |
| commit | ec2b91a6e3fe92eb088a54aa83118c96922b88a2 (patch) | |
| tree | 531acc54f36b00bcde3c4bec9e6bd93b7f4fdc2c /arch/powerpc/include | |
| parent | df633166bd6defede969fc0ef3bb1e5fdd184077 (diff) | |
| download | linux-fsl-qoriq-ec2b91a6e3fe92eb088a54aa83118c96922b88a2.tar.xz | |
KVM: PPC: e500: TLB emulation for IND entries
Handle indirect entries (IND) in TLB emulation code. Translation size of IND
entries differ from the size of referred Page Tables (Linux guests now use IND
of 2MB for 4KB PTs) and this require careful tweak of the existing logic.
TLB search emulation requires additional search in HW TLB0 (since these entries
are directly added by HTW) and found entries shoud be presented to the guest with
RPN changed from PFN to GFN. There might be more GFNs pointing to the same PFN so
the only way to get the corresponding GFN is to search it in guest's PTE. If IND
entry for the corresponding PT is not available just invalidate guest's ea and
report a tlbsx miss. This patch only implements the invalidation and let a TODO
note for searching HW TLB0.
Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
(cherry picked and merged from sdk1.5 commit fa267bdd889348c8f7f1ebd0f72173ad5c780abc)
Change-Id: Ibb3910c44a5413aa0b2ace0c858f46643c0dfa8d
Reviewed-on: http://git.am.freescale.net:8181/11561
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Stuart Yoder <stuart.yoder@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
Diffstat (limited to 'arch/powerpc/include')
| -rw-r--r-- | arch/powerpc/include/asm/mmu-book3e.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/mmu-book3e.h b/arch/powerpc/include/asm/mmu-book3e.h index 3f079ab..30f898d 100644 --- a/arch/powerpc/include/asm/mmu-book3e.h +++ b/arch/powerpc/include/asm/mmu-book3e.h @@ -60,6 +60,7 @@ #define MAS1_IPROT 0x40000000 #define MAS1_TID(x) (((x) << 16) & 0x3FFF0000) #define MAS1_IND 0x00002000 +#define MAS1_IND_SHIFT 13 #define MAS1_TS 0x00001000 #define MAS1_TSIZE_MASK 0x00000f80 #define MAS1_TSIZE_SHIFT 7 @@ -96,6 +97,7 @@ #define MAS4_TLBSEL_MASK MAS0_TLBSEL_MASK #define MAS4_TLBSELD(x) MAS0_TLBSEL(x) #define MAS4_INDD 0x00008000 /* Default IND */ +#define MAS4_INDD_SHIFT 15 #define MAS4_TSIZED(x) MAS1_TSIZE(x) #define MAS4_X0D 0x00000040 #define MAS4_X1D 0x00000020 |