diff options
| author | Scott Wood <scottwood@freescale.com> | 2014-03-26 00:33:09 (GMT) |
|---|---|---|
| committer | Jose Rivera <German.Rivera@freescale.com> | 2014-04-03 00:13:09 (GMT) |
| commit | 034ab86a74633bf838ea349944702a25bc314b35 (patch) | |
| tree | 179b4bbf097bbf1633284c64c01b9575d944d7c5 /arch/powerpc/mm | |
| parent | e69d7cf496b4a7f6dfb0c7c9acda1797c2a9e608 (diff) | |
| download | linux-fsl-qoriq-034ab86a74633bf838ea349944702a25bc314b35.tar.xz | |
powerpc/e6500: Remove A-004801 workaround
The SDK no longer supports e6500 rev1.
This reverts commit 38043080bb90f931efbe56a3f407c18206985f18
"powerpc/e6500: extend TLB miss lock to invalidations"
and commit b9e282e1347b771b736a84e6b0a1048c551e6a6c
"powerpc/e6500: add kconfig option for erratum A-004801"
Signed-off-by: Scott Wood <scottwood@freescale.com>
Change-Id: I749f497cbb6b96d045434065b869b253f01d6575
Reviewed-on: http://git.am.freescale.net:8181/10272
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Kim Phillips <Kim.Phillips@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
Diffstat (limited to 'arch/powerpc/mm')
| -rw-r--r-- | arch/powerpc/mm/tlb_nohash_low.S | 56 |
1 files changed, 0 insertions, 56 deletions
diff --git a/arch/powerpc/mm/tlb_nohash_low.S b/arch/powerpc/mm/tlb_nohash_low.S index c7a5943..ba31b2c 100644 --- a/arch/powerpc/mm/tlb_nohash_low.S +++ b/arch/powerpc/mm/tlb_nohash_low.S @@ -319,44 +319,6 @@ ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX) 1: wrtee r10 blr #elif defined(CONFIG_PPC_BOOK3E) - -#ifdef CONFIG_FSL_ERRATUM_A_004801 -.macro tlb_lock - ld r7,PACA_TLB_PER_CORE_PTR(r13) - mtocrf 0x01,r7 - addi r8,r7,PACA_TLB_LOCK-1 /* -1 to compensate for low bit set */ - bf 31,1f /* no lock if TLB_PER_CORE_HAS_LOCK clear */ -2: lbarx r9,0,r8 - cmpdi r9,0 - bne 3f - li r9,1 - stbcx. r9,0,r8 - bne 2b - .subsection 1 -3: lbz r9,0(r8) - cmpdi r9,0 - bne 3b - b 2b - .previous -1: -.endm - -.macro tlb_unlock - mtocrf 0x01,r7 - bf 31,1f /* no lock if TLB_PER_CORE_HAS_LOCK clear */ - li r9,0 - isync - stb r9,0(r8) -1: -.endm -#else -.macro tlb_lock -.endm - -.macro tlb_unlock -.endm -#endif - /* * New Book3E (>= 2.06) implementation * @@ -367,10 +329,8 @@ _GLOBAL(_tlbil_pid) slwi r4,r3,MAS6_SPID_SHIFT mfmsr r10 wrteei 0 - tlb_lock mtspr SPRN_MAS6,r4 PPC_TLBILX_PID(0,R0) - tlb_unlock wrtee r10 msync isync @@ -381,30 +341,22 @@ _GLOBAL(_tlbil_pid_noind) mfmsr r10 ori r4,r4,MAS6_SIND wrteei 0 - tlb_lock mtspr SPRN_MAS6,r4 PPC_TLBILX_PID(0,R0) - tlb_unlock wrtee r10 msync isync blr _GLOBAL(_tlbil_all) - mfmsr r10 - wrteei 0 - tlb_lock PPC_TLBILX_ALL(0,R0) msync isync - tlb_unlock - wrtee r10 blr _GLOBAL(_tlbil_va) mfmsr r10 wrteei 0 - tlb_lock cmpwi cr0,r6,0 slwi r4,r4,MAS6_SPID_SHIFT rlwimi r4,r5,MAS6_ISIZE_SHIFT,MAS6_ISIZE_MASK @@ -414,7 +366,6 @@ _GLOBAL(_tlbil_va) PPC_TLBILX_VA(0,R3) msync isync - tlb_unlock wrtee r10 blr @@ -457,10 +408,6 @@ _GLOBAL(set_context) * Load TLBCAM[index] entry in to the L2 CAM MMU */ _GLOBAL(loadcam_entry) - mfmsr r10 - wrteei 0 - tlb_lock - LOAD_REG_ADDR(r4, TLBCAM) mulli r5,r3,TLBCAM_SIZE add r3,r5,r4 @@ -479,8 +426,5 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS) isync tlbwe isync - - tlb_unlock - wrtee r10 blr #endif |