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| author | Scott Wood <scottwood@freescale.com> | 2014-05-20 04:04:55 (GMT) |
|---|---|---|
| committer | Jose Rivera <German.Rivera@freescale.com> | 2014-05-21 13:29:27 (GMT) |
| commit | cf01d1a17c2a5269f6b65c338f534cacb236e2c8 (patch) | |
| tree | c3cfb1c667506f6f8df348a9805cc6bf3910e780 /arch/powerpc/mm | |
| parent | 589b6bc9b283455d83290d6986cac9914f1c4d5f (diff) | |
| download | linux-fsl-qoriq-cf01d1a17c2a5269f6b65c338f534cacb236e2c8.tar.xz | |
powerpc/e6500: hw tablewalk: clear TID in kernel indirect entries
Previously TID was being cleared before the tlbsx, but not after. This
can lead to a multiway hit between a TLB entry with TID=0 (previously
inserted when PID=0) and a TLB entry with TID!=0 that matches PID.
This can theoretically result in undefined behavior, though we probably
get lucky due to the details of the overlap. It also results in the
inability to use multihit detection to detect other conflicting TLB
entries, as well as poorer TLB utilization due to duplicating kernel
TLB entries.
Rather than try to patch up MAS1 after tlbsx, the entire value is
saved/restored as with MAS2.
I observed a slight improvement in TLB miss performance with this patch
applied.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Reported-by: Ed Swarthout <ed.swarthout@freescale.com>
Change-Id: Ia756411e110c245781357a3b1985fade648d791a
Reviewed-on: http://git.am.freescale.net:8181/12509
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Edward L Swarthout <ed.swarthout@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
Diffstat (limited to 'arch/powerpc/mm')
| -rw-r--r-- | arch/powerpc/mm/tlb_low_64e.S | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/arch/powerpc/mm/tlb_low_64e.S b/arch/powerpc/mm/tlb_low_64e.S index b9274d5..6bc4015 100644 --- a/arch/powerpc/mm/tlb_low_64e.S +++ b/arch/powerpc/mm/tlb_low_64e.S @@ -388,19 +388,17 @@ BEGIN_FTR_SECTION .previous 1: subi r11,r11,PACA_TLB_LOCK-1 - mfspr r15,SPRN_MAS2 + mfspr r15,SPRN_MAS1 + mfspr r10,SPRN_MAS2 tlbsx 0,r16 + mtspr SPRN_MAS2,r10 mfspr r10,SPRN_MAS1 + mtspr SPRN_MAS1,r15 + andis. r10,r10,MAS1_VALID@h bne tlb_miss_done_fsl_htw - /* Undo MAS-damage from the tlbsx */ - mfspr r10,SPRN_MAS1 - oris r10,r10,MAS1_VALID@h -// ori r10,r10,MAS1_IND - mtspr SPRN_MAS1,r10 - mtspr SPRN_MAS2,r15 END_FTR_SECTION_IFSET(CPU_FTR_SMT) /* Now, we need to walk the page tables. First check if we are in |