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authorMark Brown <broonie@opensource.wolfsonmicro.com>2011-04-18 17:07:43 (GMT)
committerMark Brown <broonie@opensource.wolfsonmicro.com>2011-04-18 17:07:43 (GMT)
commitd5381e42f64ca19f05c5799ffae5708acb6ed411 (patch)
tree8b5e757a9847047102c475c6c583afc191d02e5b /arch/powerpc/oprofile/op_model_cell.c
parentf030d60b30855e18ac5bf080fa9e576147623d18 (diff)
parentb3c27b51db9112d03864fdef44fa611dd69c1425 (diff)
downloadlinux-fsl-qoriq-d5381e42f64ca19f05c5799ffae5708acb6ed411.tar.xz
ASoC: Merge branch 'for-2.6.39' into for-2.6.40
Fix trivial conflict caused by silly spelling fix patch. Conflicts: sound/soc/codecs/wm8994.c
Diffstat (limited to 'arch/powerpc/oprofile/op_model_cell.c')
-rw-r--r--arch/powerpc/oprofile/op_model_cell.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/powerpc/oprofile/op_model_cell.c b/arch/powerpc/oprofile/op_model_cell.c
index c4d2b71..cb515cf 100644
--- a/arch/powerpc/oprofile/op_model_cell.c
+++ b/arch/powerpc/oprofile/op_model_cell.c
@@ -67,7 +67,7 @@
#define MAX_SPU_COUNT 0xFFFFFF /* maximum 24 bit LFSR value */
-/* Minumum HW interval timer setting to send value to trace buffer is 10 cycle.
+/* Minimum HW interval timer setting to send value to trace buffer is 10 cycle.
* To configure counter to send value every N cycles set counter to
* 2^32 - 1 - N.
*/
@@ -1470,7 +1470,7 @@ static int cell_global_start(struct op_counter_config *ctr)
* trace buffer at the maximum rate possible. The trace buffer is configured
* to store the PCs, wrapping when it is full. The performance counter is
* initialized to the max hardware count minus the number of events, N, between
- * samples. Once the N events have occured, a HW counter overflow occurs
+ * samples. Once the N events have occurred, a HW counter overflow occurs
* causing the generation of a HW counter interrupt which also stops the
* writing of the SPU PC values to the trace buffer. Hence the last PC
* written to the trace buffer is the SPU PC that we want. Unfortunately,
@@ -1656,7 +1656,7 @@ static void cell_handle_interrupt_ppu(struct pt_regs *regs,
* The counters were frozen by the interrupt.
* Reenable the interrupt and restart the counters.
* If there was a race between the interrupt handler and
- * the virtual counter routine. The virutal counter
+ * the virtual counter routine. The virtual counter
* routine may have cleared the interrupts. Hence must
* use the virt_cntr_inter_mask to re-enable the interrupts.
*/