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author | Stephen Rothwell <sfr@canb.auug.org.au> | 2007-04-24 03:50:55 (GMT) |
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committer | Paul Mackerras <paulus@samba.org> | 2007-04-24 12:08:59 (GMT) |
commit | 8c8dc322486d5394dc981bef9276dd0ce6c8d1ce (patch) | |
tree | 2275c19196414da08a3834c4b56a1da72e1e3715 /arch/powerpc/platforms/chrp/pci.c | |
parent | 112466b4d0036b3244509d01dbbf3c8caec52a23 (diff) | |
download | linux-fsl-qoriq-8c8dc322486d5394dc981bef9276dd0ce6c8d1ce.tar.xz |
[POWERPC] Remove old interface find_path_device
Replaced by of_find_node_by_path.
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/powerpc/platforms/chrp/pci.c')
-rw-r--r-- | arch/powerpc/platforms/chrp/pci.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/arch/powerpc/platforms/chrp/pci.c b/arch/powerpc/platforms/chrp/pci.c index b23e397..de776e3 100644 --- a/arch/powerpc/platforms/chrp/pci.c +++ b/arch/powerpc/platforms/chrp/pci.c @@ -185,10 +185,9 @@ setup_python(struct pci_controller *hose, struct device_node *dev) /* Marvell Discovery II based Pegasos 2 */ static void __init setup_peg2(struct pci_controller *hose, struct device_node *dev) { - struct device_node *root = find_path_device("/"); + struct device_node *root = of_find_node_by_path("/"); struct device_node *rtas; - of_node_get(root); rtas = of_find_node_by_name (root, "rtas"); if (rtas) { hose->ops = &rtas_pci_ops; @@ -198,6 +197,7 @@ static void __init setup_peg2(struct pci_controller *hose, struct device_node *d " your firmware\n"); } pci_assign_all_buses = 1; + /* keep the reference to the root node */ } void __init @@ -210,7 +210,7 @@ chrp_find_bridges(void) const unsigned int *dma; const char *model, *machine; int is_longtrail = 0, is_mot = 0, is_pegasos = 0; - struct device_node *root = find_path_device("/"); + struct device_node *root = of_find_node_by_path("/"); struct resource r; /* * The PCI host bridge nodes on some machines don't have @@ -309,6 +309,7 @@ chrp_find_bridges(void) printk("pci_dram_offset = %lx\n", pci_dram_offset); } } + of_node_put(root); } /* SL82C105 IDE Control/Status Register */ |