diff options
author | Rich Schmitt <B43082@freescale.com> | 2014-10-31 15:03:32 (GMT) |
---|---|---|
committer | Matthew Weigel <Matthew.Weigel@freescale.com> | 2014-12-11 18:39:21 (GMT) |
commit | 0b18afe44faef1516f66168bbf782ebad4040006 (patch) | |
tree | 1c0fd882a9dd5476a835b410109ca9ebbd95278e /arch/powerpc/platforms | |
parent | 23fd3e4bab3478f2b620732c0a4e07b3567b9f1c (diff) | |
parent | bbadd4637d89b404a1b6a539ea72b37d4a748001 (diff) | |
download | linux-fsl-qoriq-0b18afe44faef1516f66168bbf782ebad4040006.tar.xz |
Integrate t1024 patches
Merge remote-tracking branch 't1024-linux/master'
Diffstat (limited to 'arch/powerpc/platforms')
-rw-r--r-- | arch/powerpc/platforms/85xx/Kconfig | 2 | ||||
-rw-r--r-- | arch/powerpc/platforms/85xx/corenet_diu.c | 105 | ||||
-rw-r--r-- | arch/powerpc/platforms/85xx/corenet_generic.c | 9 | ||||
-rw-r--r-- | arch/powerpc/platforms/85xx/deepsleep.c | 2 | ||||
-rw-r--r-- | arch/powerpc/platforms/85xx/qoriq_pm.c | 12 |
5 files changed, 120 insertions, 10 deletions
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig index ab4777a..0bc51f8 100644 --- a/arch/powerpc/platforms/85xx/Kconfig +++ b/arch/powerpc/platforms/85xx/Kconfig @@ -286,7 +286,7 @@ config CORENET_GENERIC For 64bit kernel, the following boards are supported: T208x QDS and RDB, T4240 QDS, T4240 RDB and B4 QDS The following boards are supported for both 32bit and 64bit kernel: - P5020 DS, P5040 DS, T104xQDS, T104xRDB + P5020 DS, P5040 DS, T104xQDS, T104xRDB, T102xQDS, T102xRDB endif # FSL_SOC_BOOKE diff --git a/arch/powerpc/platforms/85xx/corenet_diu.c b/arch/powerpc/platforms/85xx/corenet_diu.c index c8c322b..cb5a512 100644 --- a/arch/powerpc/platforms/85xx/corenet_diu.c +++ b/arch/powerpc/platforms/85xx/corenet_diu.c @@ -77,11 +77,93 @@ exit: } /** + * t102xqds_set_monitor_port: switch the output to a different monitor port + */ + +#define BRDCFG5 0x55 +#define BRDCFG15 0x5F +/* BRDCFG5[0:1] controls routing and use of I2C3 & I2C4 ports*/ +#define BRDCFG5_IMX_DIU_HIGH 0x80 +#define BRDCFG5_IMX_DIU_LOW 0x40 + +/* BRDCFG15[3] controls LCD Panel Powerdown*/ +#define BRDCFG15_LCD_PD 0x10 +#define BRDCFG15_LCD_ENABLED 0x80 + +/* BRDCFG15[6:7] controls DIU MUX selction*/ +#define BRDCFG15_DIUSEL_HDMI 0x03 +#define BRDCFG15_DIUSEL_LVDS 0x01 + +static void t102xqds_set_monitor_port(enum fsl_diu_monitor_port port) +{ + struct device_node *pixis_node; + void __iomem *pixis; + + pixis_node = of_find_compatible_node(NULL, NULL, "fsl,tetra-fpga"); + if (!pixis_node) { + pr_err("t102xqds: missing pixis node\n"); + goto exit; + } + + pixis = of_iomap(pixis_node, 0); + of_node_put(pixis_node); + if (!pixis) { + pr_err("t102xqds: could not map pixis registers\n"); + goto exit; + } + + /* Route I2C4 to DIU system as HSYNC/VSYNC */ + clrbits8(pixis + BRDCFG5, BRDCFG5_IMX_DIU_LOW); + setbits8(pixis + BRDCFG5, BRDCFG5_IMX_DIU_HIGH); + + switch (port) { + case FSL_DIU_PORT_DVI: + /* Enable the DVI(HDMI) port, disable the DFP and + * the backlight + */ + clrbits8(pixis + BRDCFG15, BRDCFG15_LCD_ENABLED); + setbits8(pixis + BRDCFG15, BRDCFG15_LCD_PD); + + clrbits8(pixis + BRDCFG15, BRDCFG15_DIUSEL_HDMI); + break; + case FSL_DIU_PORT_LVDS: + /* + * LVDS also needs backlight enabled, otherwise the display + * will be blank. + */ + /* Enable the DFP port, disable the DVI*/ + setbits8(pixis + BRDCFG15, BRDCFG15_DIUSEL_LVDS); + + clrbits8(pixis + BRDCFG15, BRDCFG15_LCD_PD); + setbits8(pixis + BRDCFG15, BRDCFG15_LCD_ENABLED); + break; + default: + pr_err("%s: Unsupported monitor port %i\n", __func__, port); + } + + iounmap(pixis); + +exit: + return; +} + +static const struct of_device_id scfg_matches[] = { + { + .compatible = "fsl,t1040-scfg", + }, + { + .compatible = "fsl,t1024-scfg", + }, + {}, +}; + + +/** * t1042rdb_set_pixel_clock: program the DIU's clock * * @pixclock: the wavelength, in picoseconds, of the clock */ -static void t1042rdb_set_pixel_clock(unsigned int pixclock) +static void corenet_set_pixel_clock(unsigned int pixclock) { struct device_node *scfg_np = NULL; void __iomem *scfg; @@ -90,7 +172,7 @@ static void t1042rdb_set_pixel_clock(unsigned int pixclock) u32 pxclk; /* Map the global utilities registers. */ - scfg_np = of_find_compatible_node(NULL, NULL, "fsl,t1040-scfg"); + scfg_np = of_find_matching_node_and_match(NULL, scfg_matches, NULL); if (!scfg_np) { freq = temp; pr_err("%s: Missing scfg node. Can not display video.\n", @@ -130,10 +212,10 @@ static void t1042rdb_set_pixel_clock(unsigned int pixclock) } /** - * t1042rdb_valid_monitor_port: set the monitor port for sysfs + * corenet_valid_monitor_port: set the monitor port for sysfs */ static enum fsl_diu_monitor_port -t1042rdb_valid_monitor_port(enum fsl_diu_monitor_port port) +corenet_valid_monitor_port(enum fsl_diu_monitor_port port) { switch (port) { case FSL_DIU_PORT_DVI: @@ -147,8 +229,15 @@ t1042rdb_valid_monitor_port(enum fsl_diu_monitor_port port) static void t1042rdb_diu_init(void) { diu_ops.set_monitor_port = t1042rdb_set_monitor_port; - diu_ops.set_pixel_clock = t1042rdb_set_pixel_clock; - diu_ops.valid_monitor_port = t1042rdb_valid_monitor_port; + diu_ops.set_pixel_clock = corenet_set_pixel_clock; + diu_ops.valid_monitor_port = corenet_valid_monitor_port; +} + +static void t1024qds_diu_init(void) +{ + diu_ops.set_monitor_port = t102xqds_set_monitor_port; + diu_ops.set_pixel_clock = corenet_set_pixel_clock; + diu_ops.valid_monitor_port = corenet_valid_monitor_port; } static int __init corenet_diu_init(void) @@ -163,6 +252,10 @@ static int __init corenet_diu_init(void) if (of_find_compatible_node(NULL, NULL, "fsl,T1042RDB_PI")) t1042rdb_diu_init(); + /* T1024QDS board */ + if (of_find_compatible_node(NULL, NULL, "fsl,T1024QDS")) + t1024qds_diu_init(); + return 0; } early_initcall(corenet_diu_init); diff --git a/arch/powerpc/platforms/85xx/corenet_generic.c b/arch/powerpc/platforms/85xx/corenet_generic.c index adb65a5..81fef36 100644 --- a/arch/powerpc/platforms/85xx/corenet_generic.c +++ b/arch/powerpc/platforms/85xx/corenet_generic.c @@ -54,7 +54,8 @@ void __init corenet_gen_pic_init(void) * to enable the mixed mode of MPIC. */ if ((SVR_SOC_VER(svr) == SVR_T1040) || - (SVR_SOC_VER(svr) == SVR_T1042)) { + (SVR_SOC_VER(svr) == SVR_T1042) || + (SVR_SOC_VER(svr) == SVR_T1024)) { ppc_md.get_irq = mpic_get_irq; } @@ -150,6 +151,9 @@ static const char * const boards[] __initconst = { "fsl,P4080DS", "fsl,P5020DS", "fsl,P5040DS", + "fsl,T1023QDS", + "fsl,T1024QDS", + "fsl,T1024RDB", "fsl,T1040QDS", "fsl,T1042QDS", "fsl,T1040RDB", @@ -172,6 +176,9 @@ static const char * const hv_boards[] __initconst = { "fsl,P4080DS-hv", "fsl,P5020DS-hv", "fsl,P5040DS-hv", + "fsl,T1023QDS-hv", + "fsl,T1024QDS-hv", + "fsl,T1024RDB-hv", "fsl,T1040QDS-hv", "fsl,T1042QDS-hv", "fsl,T1040RDB-hv", diff --git a/arch/powerpc/platforms/85xx/deepsleep.c b/arch/powerpc/platforms/85xx/deepsleep.c index 00e1505..cbd0c2a 100644 --- a/arch/powerpc/platforms/85xx/deepsleep.c +++ b/arch/powerpc/platforms/85xx/deepsleep.c @@ -82,7 +82,7 @@ int fsl_dp_iomap(void) if (np) { pld_flag = T1040QDS_TETRA_FLAG; } else { - np = of_find_compatible_node(NULL, NULL, "fsl,t104xrdb-cpld"); + np = of_find_compatible_node(NULL, NULL, "fsl,deepsleep-cpld"); if (np) { pld_flag = T104xRDB_CPLD_FLAG; } else { diff --git a/arch/powerpc/platforms/85xx/qoriq_pm.c b/arch/powerpc/platforms/85xx/qoriq_pm.c index 155dc28..f1ec1bd 100644 --- a/arch/powerpc/platforms/85xx/qoriq_pm.c +++ b/arch/powerpc/platforms/85xx/qoriq_pm.c @@ -154,6 +154,16 @@ static const struct platform_suspend_ops qoriq_suspend_ops = { .end = qoriq_suspend_end, }; +static const struct of_device_id deepsleep_matches[] = { + { + .compatible = "fsl,t1040-rcpm", + }, + { + .compatible = "fsl,t1024-rcpm", + }, + {}, +}; + static int __init qoriq_suspend_init(void) { struct device_node *np; @@ -165,7 +175,7 @@ static int __init qoriq_suspend_init(void) if (np) sleep_pm_state = PLAT_PM_LPM20; - np = of_find_compatible_node(NULL, NULL, "fsl,t1040-rcpm"); + np = of_find_matching_node_and_match(NULL, deepsleep_matches, NULL); if (np) { fsl_enter_deepsleep = fsl_enter_epu_deepsleep; sleep_modes |= FSL_DEEP_SLEEP; |