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| author | Wang Dongsheng <dongsheng.wang@freescale.com> | 2014-04-25 07:59:49 (GMT) |
|---|---|---|
| committer | Jose Rivera <German.Rivera@freescale.com> | 2014-04-29 16:16:59 (GMT) |
| commit | 9659e78cb8f5f086f661cd0b7f6b32bce18bbc34 (patch) | |
| tree | aa2d93f9b698239804ade8fd2ce257487f4c5ad1 /arch/powerpc/sysdev/fsl_pci.h | |
| parent | 4f7b508a0a88bf49cd4ac0747769a3dc966034ad (diff) | |
| download | linux-fsl-qoriq-9659e78cb8f5f086f661cd0b7f6b32bce18bbc34.tar.xz | |
fsl/pci: The new pci suspend/resume implementation
If we do nothing in suspend/resume, some platform PCIe ip-block
can't guarantee the link back to L0 state from sleep, then, when
we read the EP device will hang. Only we send pme turnoff message
in pci controller suspend, and send pme exit message in resume, the
link state will be normal.
When we send pme turnoff message in pci controller suspend, the
links will into l2/l3 ready, then, host cannot communicate with
ep device, but pci-driver will call back EP device to save them
state. So we need to change platform_driver->suspend/resume to
syscore->suspend/resume.
So the new suspend/resume implementation, send pme turnoff message
in suspend, and send pme exit message in resume. And add a PME handler,
to response PME & message interrupt.
Change platform_driver->suspend/resume to syscore->suspend/resume.
pci-driver will call back EP device, to save EP state in
pci_pm_suspend_noirq, so we need to keep the link, until
pci_pm_suspend_noirq finish.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Change-Id: Id82d2e92994e466de1b2a4eb9ecef73c112ec753
Reviewed-on: http://git.am.freescale.net:8181/11538
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Yang Li <LeoLi@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
Diffstat (limited to 'arch/powerpc/sysdev/fsl_pci.h')
| -rw-r--r-- | arch/powerpc/sysdev/fsl_pci.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h index f1b39d9..5d74092 100644 --- a/arch/powerpc/sysdev/fsl_pci.h +++ b/arch/powerpc/sysdev/fsl_pci.h @@ -32,6 +32,16 @@ struct platform_device; #define PIWAR_WRITE_SNOOP 0x00005000 #define PIWAR_SZ_MASK 0x0000003f +#define PEX_PMCR_PTOMR 0x1 +#define PEX_PMCR_EXL2S 0x2 + +#define PME_DISR_EN_PTOD 0x00008000 +#define PME_DISR_EN_ENL23D 0x00002000 +#define PME_DISR_EN_EXL23D 0x00001000 + +#define ENL23_DETECT_BIT 0x00002000 +#define EXL23_DETECT_BIT 0x00001000 + #define PAOR_LIODON_MODE 1 /* To access LIODN permission table */ #define PAOR_MSIX_VECTOR_MODE 2 /* To access MSI-X table structure */ #define PAOR_MSIX_PBA_MODE 3 /* To access MSI-X PBA structure */ @@ -193,6 +203,7 @@ struct vf_atmu_regs { extern int fsl_add_bridge(struct platform_device *pdev, int is_primary); extern void fsl_pcibios_fixup_bus(struct pci_bus *bus); +void fsl_pcibios_fixup_phb(struct pci_controller *phb); extern int mpc83xx_add_bridge(struct device_node *dev); u64 fsl_pci_immrbar_base(struct pci_controller *hose); @@ -206,6 +217,10 @@ void fsl_pci_assign_primary(void); static inline void fsl_pci_assign_primary(void) {} #endif +#ifdef CONFIG_P1022_DS +void p1022ds_reset_pcie_slot(void); +#endif + #ifdef CONFIG_EDAC_MPC85XX int mpc85xx_pci_err_probe(struct platform_device *op); #else |