diff options
author | Kumar Gala <galak@kernel.crashing.org> | 2007-10-04 06:04:57 (GMT) |
---|---|---|
committer | Kumar Gala <galak@kernel.crashing.org> | 2007-10-08 13:38:47 (GMT) |
commit | e1c1575f831ab2165732037e6d664010a0149730 (patch) | |
tree | ecfc90b06eb4b7402a3334ebe6b8287e73abc671 /arch/powerpc/sysdev/fsl_soc.c | |
parent | c9438affcb7ac0dda4c6c6961637fb272f7c32d4 (diff) | |
download | linux-fsl-qoriq-e1c1575f831ab2165732037e6d664010a0149730.tar.xz |
[POWERPC] 85xx/86xx: refactor RSTCR reset code
On the majority of 85xx & 86xx we have a register that's ability to
assert HRESET_REQ to reset the board. We refactored that code so it
can be shared between both platforms into fsl_soc.c and removed all
the duplication in each platform directory.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/sysdev/fsl_soc.c')
-rw-r--r-- | arch/powerpc/sysdev/fsl_soc.c | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/arch/powerpc/sysdev/fsl_soc.c b/arch/powerpc/sysdev/fsl_soc.c index c765d7a..be5e0bd 100644 --- a/arch/powerpc/sysdev/fsl_soc.c +++ b/arch/powerpc/sysdev/fsl_soc.c @@ -1298,3 +1298,41 @@ err: return spi_register_board_info(board_infos, num_board_infos); } + +#if defined(CONFIG_PPC_85xx) || defined(CONFIG_PPC_86xx) +static __be32 __iomem *rstcr; + +static int __init setup_rstcr(void) +{ + struct device_node *np; + np = of_find_node_by_name(NULL, "global-utilities"); + if ((np && of_get_property(np, "fsl,has-rstcr", NULL))) { + const u32 *prop = of_get_property(np, "reg", NULL); + if (prop) { + /* map reset control register + * 0xE00B0 is offset of reset control register + */ + rstcr = ioremap(get_immrbase() + *prop + 0xB0, 0xff); + if (!rstcr) + printk (KERN_EMERG "Error: reset control " + "register not mapped!\n"); + } + } else + printk (KERN_INFO "rstcr compatible register does not exist!\n"); + if (np) + of_node_put(np); + return 0; +} + +arch_initcall(setup_rstcr); + +void fsl_rstcr_restart(char *cmd) +{ + local_irq_disable(); + if (rstcr) + /* set reset control register */ + out_be32(rstcr, 0x2); /* HRESET_REQ */ + + while (1) ; +} +#endif |