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| author | Minghuan Lian <Minghuan.Lian@freescale.com> | 2013-07-31 02:59:07 (GMT) |
|---|---|---|
| committer | Scott Wood <scottwood@freescale.com> | 2014-04-08 00:01:45 (GMT) |
| commit | 09f66e382b14c265895a6e04bcaab82304565edc (patch) | |
| tree | 6e3ecf6ea60c6459f09c2790e53875c683a6f435 /arch/powerpc | |
| parent | 7405060efa996c6ec23412beb3902ce08d2af3c5 (diff) | |
| download | linux-fsl-qoriq-09f66e382b14c265895a6e04bcaab82304565edc.tar.xz | |
powerpc/dts: fix sRIO error interrupt for b4860
For B4 platform, MPIC EISR register is in reversed bitmap order,
instead of "Error interrupt source 0-31. Bit 0 represents SRC0."
the correct ordering is "Error interrupt source 0-31. Bit 0
represents SRC31." This patch is to fix sRIO EISR bit value
of error interrupt in dts node.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
(cherry picked from commit 0e3d4373b8a7757a8f5187f5cabafb6aceff469b)
Diffstat (limited to 'arch/powerpc')
| -rw-r--r-- | arch/powerpc/boot/dts/fsl/b4860si-post.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi index e5cf6c8..9813975 100644 --- a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi @@ -41,7 +41,7 @@ &rio { compatible = "fsl,srio"; - interrupts = <16 2 1 11>; + interrupts = <16 2 1 20>; #address-cells = <2>; #size-cells = <2>; fsl,iommu-parent = <&pamu0>; |