diff options
| author | Mihai Caraman <mihai.caraman@freescale.com> | 2013-09-12 13:55:44 (GMT) |
|---|---|---|
| committer | Rivera Jose-B46482 <German.Rivera@freescale.com> | 2013-09-13 19:28:01 (GMT) |
| commit | 42de4617f9262df22215101268f497c58bf2bee4 (patch) | |
| tree | d0b52e5cb806be0cf678a14db3fdae3268934d10 /arch/powerpc | |
| parent | 4e8d900975c1f2ddab903ad103af92f56de678c1 (diff) | |
| download | linux-fsl-qoriq-42de4617f9262df22215101268f497c58bf2bee4.tar.xz | |
KVM: PPC: e500: Fix default TLB for victim hint
TLB search for victim hint in KVM relied on host to set default TLB.
When hardware tablewalk support is enabled the kernel sets TLB0 as
default which led KVM to evict the bolted entry.
Set and restore the default TLB when searching for victim hint.
Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
Change-Id: Idaa65fda62787a2b9b02641649b8c411ffe458fa
Reviewed-on: http://git.am.freescale.net:8181/4698
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com>
Reviewed-by: Rivera Jose-B46482 <German.Rivera@freescale.com>
Diffstat (limited to 'arch/powerpc')
| -rw-r--r-- | arch/powerpc/include/asm/mmu-book3e.h | 1 | ||||
| -rw-r--r-- | arch/powerpc/kvm/e500_mmu_host.c | 4 |
2 files changed, 5 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/mmu-book3e.h b/arch/powerpc/include/asm/mmu-book3e.h index 32e470e..dcc733c 100644 --- a/arch/powerpc/include/asm/mmu-book3e.h +++ b/arch/powerpc/include/asm/mmu-book3e.h @@ -90,6 +90,7 @@ #define MAS3_SPSIZE 0x0000003e #define MAS3_SPSIZE_SHIFT 1 +#define MAS4_TLBSEL_MASK MAS0_TLBSEL_MASK #define MAS4_TLBSELD(x) MAS0_TLBSEL(x) #define MAS4_INDD 0x00008000 /* Default IND */ #define MAS4_TSIZED(x) MAS1_TSIZE(x) diff --git a/arch/powerpc/kvm/e500_mmu_host.c b/arch/powerpc/kvm/e500_mmu_host.c index 64de70a..9f87220 100644 --- a/arch/powerpc/kvm/e500_mmu_host.c +++ b/arch/powerpc/kvm/e500_mmu_host.c @@ -118,11 +118,15 @@ static u32 get_host_mas0(unsigned long eaddr) { unsigned long flags; u32 mas0; + u32 mas4; local_irq_save(flags); mtspr(SPRN_MAS6, 0); + mas4 = mfspr(SPRN_MAS4); + mtspr(SPRN_MAS4, mas4 & ~MAS4_TLBSEL_MASK); asm volatile("tlbsx 0, %0" : : "b" (eaddr & ~CONFIG_PAGE_OFFSET)); mas0 = mfspr(SPRN_MAS0); + mtspr(SPRN_MAS4, mas4); local_irq_restore(flags); return mas0; |