diff options
| author | Eugene Surovegin <ebs@ebshome.net> | 2005-07-30 05:59:19 (GMT) |
|---|---|---|
| committer | Linus Torvalds <torvalds@g5.osdl.org> | 2005-07-30 17:14:46 (GMT) |
| commit | 5ce17b18e16177dd6409dabd38df5c2c9b58fc2d (patch) | |
| tree | cbc4e6bac2af443d9c2746c260275fc0b4d9c70b /arch/ppc/platforms/4xx/ocotea.c | |
| parent | e310fd43256b3cf4d37f6447b8f7413ca744657a (diff) | |
| download | linux-fsl-qoriq-5ce17b18e16177dd6409dabd38df5c2c9b58fc2d.tar.xz | |
[PATCH] ppc32: fix 44x early serial debug for configurations with more than 512M of RAM
Fix 44x early serial debugging for big RAM configurations (more than 512M).
We cannot use default OpenBIOS virtual mapping, because it interferes with
pinned TLB entry.
While we are at it, move early UART mapping to TLB slot 0, so it can
survive longer during boot process (slot 1 is used by the first ioremap
call, effectively killing UART mapping if it occupies this slot). Also,
change UART TLB entry size to 4K (256M is too much for a bunch of registers
:). Squash some warnings on the way.
Tested on Ebony and Ocotea with 1G of RAM.
Thanks to Scott Coulter <scott.coulter@cyclone.com> for diagnosing this
problem.
Signed-off-by: Eugene Surovegin <ebs@ebshome.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/ppc/platforms/4xx/ocotea.c')
| -rw-r--r-- | arch/ppc/platforms/4xx/ocotea.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/ppc/platforms/4xx/ocotea.c b/arch/ppc/platforms/4xx/ocotea.c index 5f82a6b..8fc34a3 100644 --- a/arch/ppc/platforms/4xx/ocotea.c +++ b/arch/ppc/platforms/4xx/ocotea.c @@ -48,6 +48,7 @@ #include <asm/bootinfo.h> #include <asm/ppc4xx_pic.h> #include <asm/ppcboot.h> +#include <asm/tlbflush.h> #include <syslib/gen550.h> #include <syslib/ibm440gx_common.h> @@ -266,6 +267,9 @@ ocotea_early_serial_map(void) #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) /* Configure debug serial access */ gen550_init(0, &port); + + /* Purge TLB entry added in head_44x.S for early serial access */ + _tlbie(UART0_IO_BASE); #endif port.membase = ioremap64(PPC440GX_UART1_ADDR, 8); |