diff options
author | Paul Mundt <lethal@linux-sh.org> | 2007-11-22 07:29:10 (GMT) |
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committer | Paul Mundt <lethal@linux-sh.org> | 2008-01-28 04:18:55 (GMT) |
commit | b6d7b666097e79a8908e3c43fd55fd291a95e133 (patch) | |
tree | 61ab633feecd144d129fc3b220ecb9376c7949bd /arch/sh/drivers/pci/pci-sh5.c | |
parent | d5f68c6dbda8e63df258a0c639f03d7565cf1d50 (diff) | |
download | linux-fsl-qoriq-b6d7b666097e79a8908e3c43fd55fd291a95e133.tar.xz |
sh: Get the SH-5 PCI support building.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/drivers/pci/pci-sh5.c')
-rw-r--r-- | arch/sh/drivers/pci/pci-sh5.c | 452 |
1 files changed, 72 insertions, 380 deletions
diff --git a/arch/sh/drivers/pci/pci-sh5.c b/arch/sh/drivers/pci/pci-sh5.c index b4d9534..a00a4df 100644 --- a/arch/sh/drivers/pci/pci-sh5.c +++ b/arch/sh/drivers/pci/pci-sh5.c @@ -18,40 +18,14 @@ #include <linux/pci.h> #include <linux/delay.h> #include <linux/types.h> -#include <asm/pci.h> #include <linux/irq.h> - +#include <asm/cpu/irq.h> +#include <asm/pci.h> #include <asm/io.h> -#include <asm/hardware.h> -#include "pci_sh5.h" - -static unsigned long pcicr_virt; -unsigned long pciio_virt; - -static void __init pci_fixup_ide_bases(struct pci_dev *d) -{ - int i; - - /* - * PCI IDE controllers use non-standard I/O port decoding, respect it. - */ - if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE) - return; - printk("PCI: IDE base address fixup for %s\n", pci_name(d)); - for(i=0; i<4; i++) { - struct resource *r = &d->resource[i]; - if ((r->start & ~0x80) == 0x374) { - r->start |= 2; - r->end = r->start; - } - } -} -DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases); +#include "pci-sh5.h" -char * __devinit pcibios_setup(char *str) -{ - return str; -} +unsigned long pcicr_virt; +unsigned long PCI_IO_AREA; /* Rounds a number UP to the nearest power of two. Used for * sizing the PCI window. @@ -79,31 +53,73 @@ static u32 __init r2p2(u32 num) return tmp; } -extern unsigned long long memory_start, memory_end; +static irqreturn_t pcish5_err_irq(int irq, void *dev_id) +{ + struct pt_regs *regs = get_irq_regs(); + unsigned pci_int, pci_air, pci_cir, pci_aint; + + pci_int = SH5PCI_READ(INT); + pci_cir = SH5PCI_READ(CIR); + pci_air = SH5PCI_READ(AIR); -int __init sh5pci_init(unsigned memStart, unsigned memSize) + if (pci_int) { + printk("PCI INTERRUPT (at %08llx)!\n", regs->pc); + printk("PCI INT -> 0x%x\n", pci_int & 0xffff); + printk("PCI AIR -> 0x%x\n", pci_air); + printk("PCI CIR -> 0x%x\n", pci_cir); + SH5PCI_WRITE(INT, ~0); + } + + pci_aint = SH5PCI_READ(AINT); + if (pci_aint) { + printk("PCI ARB INTERRUPT!\n"); + printk("PCI AINT -> 0x%x\n", pci_aint); + printk("PCI AIR -> 0x%x\n", pci_air); + printk("PCI CIR -> 0x%x\n", pci_cir); + SH5PCI_WRITE(AINT, ~0); + } + + return IRQ_HANDLED; +} + +static irqreturn_t pcish5_serr_irq(int irq, void *dev_id) +{ + printk("SERR IRQ\n"); + + return IRQ_NONE; +} + +int __init sh5pci_init(unsigned long memStart, unsigned long memSize) { u32 lsr0; u32 uval; + if (request_irq(IRQ_ERR, pcish5_err_irq, + IRQF_DISABLED, "PCI Error",NULL) < 0) { + printk(KERN_ERR "PCISH5: Cannot hook PCI_PERR interrupt\n"); + return -EINVAL; + } + + if (request_irq(IRQ_SERR, pcish5_serr_irq, + IRQF_DISABLED, "PCI SERR interrupt", NULL) < 0) { + printk(KERN_ERR "PCISH5: Cannot hook PCI_SERR interrupt\n"); + return -EINVAL; + } + pcicr_virt = onchip_remap(SH5PCI_ICR_BASE, 1024, "PCICR"); if (!pcicr_virt) { panic("Unable to remap PCICR\n"); } - pciio_virt = onchip_remap(SH5PCI_IO_BASE, 0x10000, "PCIIO"); - if (!pciio_virt) { + PCI_IO_AREA = onchip_remap(SH5PCI_IO_BASE, 0x10000, "PCIIO"); + if (!PCI_IO_AREA) { panic("Unable to remap PCIIO\n"); } - pr_debug("Register base addres is 0x%08lx\n", pcicr_virt); - /* Clear snoop registers */ SH5PCI_WRITE(CSCR0, 0); SH5PCI_WRITE(CSCR1, 0); - pr_debug("Wrote to reg\n"); - /* Switch off interrupts */ SH5PCI_WRITE(INTM, 0); SH5PCI_WRITE(AINTM, 0); @@ -113,16 +129,17 @@ int __init sh5pci_init(unsigned memStart, unsigned memSize) uval = SH5PCI_READ(CR); /* Set command Register */ - SH5PCI_WRITE(CR, uval | CR_LOCK_MASK | CR_CFINT| CR_FTO | CR_PFE | CR_PFCS | CR_BMAM); + SH5PCI_WRITE(CR, uval | CR_LOCK_MASK | CR_CFINT| CR_FTO | CR_PFE | + CR_PFCS | CR_BMAM); uval=SH5PCI_READ(CR); - pr_debug("CR is actually 0x%08x\n",uval); /* Allow it to be a master */ /* NB - WE DISABLE I/O ACCESS to stop overlap */ /* set WAIT bit to enable stepping, an attempt to improve stability */ SH5PCI_WRITE_SHORT(CSR_CMD, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_WAIT); + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | + PCI_COMMAND_WAIT); /* ** Set translation mapping memory in order to convert the address @@ -143,32 +160,30 @@ int __init sh5pci_init(unsigned memStart, unsigned memSize) SH5PCI_WRITE(IOBR,0x0); - pr_debug("PCI:Writing 0x%08x to IOBR\n",0); - /* Set up a 256K window. Totally pointless waste of address space */ SH5PCI_WRITE(IOBMR,0); - pr_debug("PCI:Writing 0x%08x to IOBMR\n",0); - /* The SH5 has a HUGE 256K I/O region, which breaks the PCI spec. Ideally, - * we would want to map the I/O region somewhere, but it is so big this is not - * that easy! + /* The SH5 has a HUGE 256K I/O region, which breaks the PCI spec. + * Ideally, we would want to map the I/O region somewhere, but it + * is so big this is not that easy! */ SH5PCI_WRITE(CSR_IBAR0,~0); /* Set memory size value */ memSize = memory_end - memory_start; - /* Now we set up the mbars so the PCI bus can see the memory of the machine */ - if (memSize < (1024 * 1024)) { - printk(KERN_ERR "PCISH5: Ridiculous memory size of 0x%x?\n", memSize); + /* Now we set up the mbars so the PCI bus can see the memory of + * the machine */ + if (memSize < (1024 * 1024)) { + printk(KERN_ERR "PCISH5: Ridiculous memory size of 0x%lx?\n", + memSize); return -EINVAL; } /* Set LSR 0 */ - lsr0 = (memSize > (512 * 1024 * 1024)) ? 0x1ff00001 : ((r2p2(memSize) - 0x100000) | 0x1); + lsr0 = (memSize > (512 * 1024 * 1024)) ? 0x1ff00001 : + ((r2p2(memSize) - 0x100000) | 0x1); SH5PCI_WRITE(LSR0, lsr0); - pr_debug("PCI:Writing 0x%08x to LSR0\n",lsr0); - /* Set MBAR 0 */ SH5PCI_WRITE(CSR_MBAR0, memory_start); SH5PCI_WRITE(LAR0, memory_start); @@ -177,334 +192,21 @@ int __init sh5pci_init(unsigned memStart, unsigned memSize) SH5PCI_WRITE(LAR1,0); SH5PCI_WRITE(LSR1,0); - pr_debug("PCI:Writing 0x%08llx to CSR_MBAR0\n",memory_start); - pr_debug("PCI:Writing 0x%08llx to LAR0\n",memory_start); - /* Enable the PCI interrupts on the device */ SH5PCI_WRITE(INTM, ~0); SH5PCI_WRITE(AINTM, ~0); SH5PCI_WRITE(PINTM, ~0); - pr_debug("Switching on all error interrupts\n"); - - return(0); -} - -static int sh5pci_read(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 *val) -{ - SH5PCI_WRITE(PAR, CONFIG_CMD(bus, devfn, where)); - - switch (size) { - case 1: - *val = (u8)SH5PCI_READ_BYTE(PDR + (where & 3)); - break; - case 2: - *val = (u16)SH5PCI_READ_SHORT(PDR + (where & 2)); - break; - case 4: - *val = SH5PCI_READ(PDR); - break; - } - - return PCIBIOS_SUCCESSFUL; -} - -static int sh5pci_write(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 val) -{ - SH5PCI_WRITE(PAR, CONFIG_CMD(bus, devfn, where)); - - switch (size) { - case 1: - SH5PCI_WRITE_BYTE(PDR + (where & 3), (u8)val); - break; - case 2: - SH5PCI_WRITE_SHORT(PDR + (where & 2), (u16)val); - break; - case 4: - SH5PCI_WRITE(PDR, val); - break; - } - - return PCIBIOS_SUCCESSFUL; -} - -static struct pci_ops pci_config_ops = { - .read = sh5pci_read, - .write = sh5pci_write, -}; - -/* Everything hangs off this */ -static struct pci_bus *pci_root_bus; - - -static u8 __init no_swizzle(struct pci_dev *dev, u8 * pin) -{ - pr_debug("swizzle for dev %d on bus %d slot %d pin is %d\n", - dev->devfn,dev->bus->number, PCI_SLOT(dev->devfn),*pin); - return PCI_SLOT(dev->devfn); -} - -static inline u8 bridge_swizzle(u8 pin, u8 slot) -{ - return (((pin-1) + slot) % 4) + 1; -} - -u8 __init common_swizzle(struct pci_dev *dev, u8 *pinp) -{ - if (dev->bus->number != 0) { - u8 pin = *pinp; - do { - pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn)); - /* Move up the chain of bridges. */ - dev = dev->bus->self; - } while (dev->bus->self); - *pinp = pin; - - /* The slot is the slot of the last bridge. */ - } - - return PCI_SLOT(dev->devfn); -} - -/* This needs to be shunted out of here into the board specific bit */ - -static int __init map_cayman_irq(struct pci_dev *dev, u8 slot, u8 pin) -{ - int result = -1; - - /* The complication here is that the PCI IRQ lines from the Cayman's 2 - 5V slots get into the CPU via a different path from the IRQ lines - from the 3 3.3V slots. Thus, we have to detect whether the card's - interrupts go via the 5V or 3.3V path, i.e. the 'bridge swizzling' - at the point where we cross from 5V to 3.3V is not the normal case. - - The added complication is that we don't know that the 5V slots are - always bus 2, because a card containing a PCI-PCI bridge may be - plugged into a 3.3V slot, and this changes the bus numbering. - - Also, the Cayman has an intermediate PCI bus that goes a custom - expansion board header (and to the secondary bridge). This bus has - never been used in practice. - - The 1ary onboard PCI-PCI bridge is device 3 on bus 0 - The 2ary onboard PCI-PCI bridge is device 0 on the 2ary bus of the 1ary bridge. - */ - - struct slot_pin { - int slot; - int pin; - } path[4]; - int i=0; - - while (dev->bus->number > 0) { - - slot = path[i].slot = PCI_SLOT(dev->devfn); - pin = path[i].pin = bridge_swizzle(pin, slot); - dev = dev->bus->self; - i++; - if (i > 3) panic("PCI path to root bus too long!\n"); - } - - slot = PCI_SLOT(dev->devfn); - /* This is the slot on bus 0 through which the device is eventually - reachable. */ - - /* Now work back up. */ - if ((slot < 3) || (i == 0)) { - /* Bus 0 (incl. PCI-PCI bridge itself) : perform the final - swizzle now. */ - result = IRQ_INTA + bridge_swizzle(pin, slot) - 1; - } else { - i--; - slot = path[i].slot; - pin = path[i].pin; - if (slot > 0) { - panic("PCI expansion bus device found - not handled!\n"); - } else { - if (i > 0) { - /* 5V slots */ - i--; - slot = path[i].slot; - pin = path[i].pin; - /* 'pin' was swizzled earlier wrt slot, don't do it again. */ - result = IRQ_P2INTA + (pin - 1); - } else { - /* IRQ for 2ary PCI-PCI bridge : unused */ - result = -1; - } - } - } - - return result; -} - -static irqreturn_t pcish5_err_irq(int irq, void *dev_id) -{ - struct pt_regs *regs = get_irq_regs(); - unsigned pci_int, pci_air, pci_cir, pci_aint; - - pci_int = SH5PCI_READ(INT); - pci_cir = SH5PCI_READ(CIR); - pci_air = SH5PCI_READ(AIR); - - if (pci_int) { - printk("PCI INTERRUPT (at %08llx)!\n", regs->pc); - printk("PCI INT -> 0x%x\n", pci_int & 0xffff); - printk("PCI AIR -> 0x%x\n", pci_air); - printk("PCI CIR -> 0x%x\n", pci_cir); - SH5PCI_WRITE(INT, ~0); - } - - pci_aint = SH5PCI_READ(AINT); - if (pci_aint) { - printk("PCI ARB INTERRUPT!\n"); - printk("PCI AINT -> 0x%x\n", pci_aint); - printk("PCI AIR -> 0x%x\n", pci_air); - printk("PCI CIR -> 0x%x\n", pci_cir); - SH5PCI_WRITE(AINT, ~0); - } - - return IRQ_HANDLED; -} - -static irqreturn_t pcish5_serr_irq(int irq, void *dev_id) -{ - printk("SERR IRQ\n"); - - return IRQ_NONE; -} - -static void __init -pcibios_size_bridge(struct pci_bus *bus, struct resource *ior, - struct resource *memr) -{ - struct resource io_res, mem_res; - struct pci_dev *dev; - struct pci_dev *bridge = bus->self; - struct list_head *ln; - - if (!bridge) - return; /* host bridge, nothing to do */ - - /* set reasonable default locations for pcibios_align_resource */ - io_res.start = PCIBIOS_MIN_IO; - mem_res.start = PCIBIOS_MIN_MEM; - - io_res.end = io_res.start; - mem_res.end = mem_res.start; - - /* Collect information about how our direct children are layed out. */ - for (ln=bus->devices.next; ln != &bus->devices; ln=ln->next) { - int i; - dev = pci_dev_b(ln); - - /* Skip bridges for now */ - if (dev->class >> 8 == PCI_CLASS_BRIDGE_PCI) - continue; - - for (i = 0; i < PCI_NUM_RESOURCES; i++) { - struct resource res; - unsigned long size; - - memcpy(&res, &dev->resource[i], sizeof(res)); - size = res.end - res.start + 1; - - if (res.flags & IORESOURCE_IO) { - res.start = io_res.end; - pcibios_align_resource(dev, &res, size, 0); - io_res.end = res.start + size; - } else if (res.flags & IORESOURCE_MEM) { - res.start = mem_res.end; - pcibios_align_resource(dev, &res, size, 0); - mem_res.end = res.start + size; - } - } - } - - /* And for all of the subordinate busses. */ - for (ln=bus->children.next; ln != &bus->children; ln=ln->next) - pcibios_size_bridge(pci_bus_b(ln), &io_res, &mem_res); - - /* turn the ending locations into sizes (subtract start) */ - io_res.end -= io_res.start; - mem_res.end -= mem_res.start; - - /* Align the sizes up by bridge rules */ - io_res.end = ALIGN(io_res.end, 4*1024) - 1; - mem_res.end = ALIGN(mem_res.end, 1*1024*1024) - 1; - - /* Adjust the bridge's allocation requirements */ - bridge->resource[0].end = bridge->resource[0].start + io_res.end; - bridge->resource[1].end = bridge->resource[1].start + mem_res.end; - - bridge->resource[PCI_BRIDGE_RESOURCES].end = - bridge->resource[PCI_BRIDGE_RESOURCES].start + io_res.end; - bridge->resource[PCI_BRIDGE_RESOURCES+1].end = - bridge->resource[PCI_BRIDGE_RESOURCES+1].start + mem_res.end; - - /* adjust parent's resource requirements */ - if (ior) { - ior->end = ALIGN(ior->end, 4*1024); - ior->end += io_res.end; - } - - if (memr) { - memr->end = ALIGN(memr->end, 1*1024*1024); - memr->end += mem_res.end; - } -} - -static void __init pcibios_size_bridges(void) -{ - struct resource io_res, mem_res; - - memset(&io_res, 0, sizeof(io_res)); - memset(&mem_res, 0, sizeof(mem_res)); - - pcibios_size_bridge(pci_root_bus, &io_res, &mem_res); -} - -static int __init pcibios_init(void) -{ - if (request_irq(IRQ_ERR, pcish5_err_irq, - IRQF_DISABLED, "PCI Error",NULL) < 0) { - printk(KERN_ERR "PCISH5: Cannot hook PCI_PERR interrupt\n"); - return -EINVAL; - } - - if (request_irq(IRQ_SERR, pcish5_serr_irq, - IRQF_DISABLED, "PCI SERR interrupt", NULL) < 0) { - printk(KERN_ERR "PCISH5: Cannot hook PCI_SERR interrupt\n"); - return -EINVAL; - } - - /* The pci subsystem needs to know where memory is and how much - * of it there is. I've simply made these globals. A better mechanism - * is probably needed. - */ - sh5pci_init(__pa(memory_start), - __pa(memory_end) - __pa(memory_start)); - - pci_root_bus = pci_scan_bus(0, &pci_config_ops, NULL); - pcibios_size_bridges(); - pci_assign_unassigned_resources(); - pci_fixup_irqs(no_swizzle, map_cayman_irq); - return 0; } -subsys_initcall(pcibios_init); - void __devinit pcibios_fixup_bus(struct pci_bus *bus) { struct pci_dev *dev = bus->self; int i; -#if 1 - if(dev) { - for(i=0; i<3; i++) { + if (dev) { + for (i= 0; i < 3; i++) { bus->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; bus->resource[i]->name = bus->name; @@ -514,23 +216,13 @@ void __devinit pcibios_fixup_bus(struct pci_bus *bus) /* For now, propagate host limits to the bus; * we'll adjust them later. */ - -#if 1 bus->resource[0]->end = 64*1024 - 1 ; bus->resource[1]->end = PCIBIOS_MIN_MEM+(256*1024*1024)-1; bus->resource[0]->start = PCIBIOS_MIN_IO; bus->resource[1]->start = PCIBIOS_MIN_MEM; -#else - bus->resource[0]->end = 0; - bus->resource[1]->end = 0; - bus->resource[0]->start =0; - bus->resource[1]->start = 0; -#endif + /* Turn off downstream PF memory address range by default */ bus->resource[2]->start = 1024*1024; bus->resource[2]->end = bus->resource[2]->start - 1; } -#endif - } - |