Merge master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6

* master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6: (35 commits)
  sh: rts7751r2d board updates.
  sh: Kill off dead bigsur and ec3104 boards.
  sh: Fixup r7780rp pata_platform for devres conversion.
  sh: Revert TLB miss fast-path changes that broke PTEA parts.
  sh: Compile fix for heartbeat consolidation.
  sh: heartbeat consolidation for banked LEDs.
  sh: define dma noncoherent API functions.
  sh: Missing flush_dcache_all() proto in cacheflush.h.
  sh: Kill dead/unused ISA code from __ioremap().
  sh: Add cpu-features header to asm/Kbuild.
  sh: Move __KERNEL__ up in asm/page.h.
  sh: Fix syscall numbering breakage.
  sh: dcache write-back for R7780RP PIO.
  sh: Switch to local TLB flush variants in additional callsites.
  sh: Local TLB flushing variants for SMP prep.
  sh: Fixup cpu_data references for the non-boot CPUs.
  sh: Use a per-cpu ASID cache.
  sh: add SH_CLK_MD Kconfig default.
  sh: Fixup SHMIN INTC register definitions.
  sh: SH-DMAC compile fixes
  ...

1 files changed, 16 insertions, 16 deletions

diff --git a/arch/sh/kernel/cpu/sh2/probe.c b/arch/sh/kernel/cpu/sh2/probe.c
index ba527d9..108e81b 100644
--- a/arch/sh/kernel/cpu/sh2/probe.c
+++ b/arch/sh/kernel/cpu/sh2/probe.c
@@ -18,27 +18,27 @@
 int __init detect_cpu_and_cache_system(void)
 {
 #if defined(CONFIG_CPU_SUBTYPE_SH7604)
-	cpu_data->type			= CPU_SH7604;
-	cpu_data->dcache.ways		= 4;
-	cpu_data->dcache.way_incr	= (1<<10);
-	cpu_data->dcache.sets		= 64;
-	cpu_data->dcache.entry_shift	= 4;
-	cpu_data->dcache.linesz		= L1_CACHE_BYTES;
-	cpu_data->dcache.flags		= 0;
+	current_cpu_data.type			= CPU_SH7604;
+	current_cpu_data.dcache.ways		= 4;
+	current_cpu_data.dcache.way_incr	= (1<<10);
+	current_cpu_data.dcache.sets		= 64;
+	current_cpu_data.dcache.entry_shift	= 4;
+	current_cpu_data.dcache.linesz		= L1_CACHE_BYTES;
+	current_cpu_data.dcache.flags		= 0;
 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
-	cpu_data->type			= CPU_SH7619;
-	cpu_data->dcache.ways		= 4;
-	cpu_data->dcache.way_incr	= (1<<12);
-	cpu_data->dcache.sets		= 256;
-	cpu_data->dcache.entry_shift	= 4;
-	cpu_data->dcache.linesz		= L1_CACHE_BYTES;
-	cpu_data->dcache.flags		= 0;
+	current_cpu_data.type			= CPU_SH7619;
+	current_cpu_data.dcache.ways		= 4;
+	current_cpu_data.dcache.way_incr	= (1<<12);
+	current_cpu_data.dcache.sets		= 256;
+	current_cpu_data.dcache.entry_shift	= 4;
+	current_cpu_data.dcache.linesz		= L1_CACHE_BYTES;
+	current_cpu_data.dcache.flags		= 0;
 #endif
 	/*
 	 * SH-2 doesn't have separate caches
 	 */
-	cpu_data->dcache.flags |= SH_CACHE_COMBINED;
-	cpu_data->icache = cpu_data->dcache;
+	current_cpu_data.dcache.flags |= SH_CACHE_COMBINED;
+	current_cpu_data.icache = current_cpu_data.dcache;
 
 	return 0;
 }