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| author | Paul Mundt <lethal@linux-sh.org> | 2009-08-15 03:29:49 (GMT) |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2009-08-15 03:29:49 (GMT) |
| commit | 37443ef3f0406e855e169c87ae3f4ffb4b6ff635 (patch) | |
| tree | dd57e6fe91e6058b45660b6e4629249a50bc448e /arch/sh/mm/cache-sh5.c | |
| parent | 916e97834e023f89b31f796b53cc9c7956e7fe17 (diff) | |
| download | linux-fsl-qoriq-37443ef3f0406e855e169c87ae3f4ffb4b6ff635.tar.xz | |
sh: Migrate SH-4 cacheflush ops to function pointers.
This paves the way for allowing individual CPUs to overload the
individual flushing routines that they care about without having to
depend on weak aliases. SH-4 is converted over initially, as it wires
up pretty much everything. The majority of the other CPUs will simply use
the default no-op implementation with their own region flushers wired up.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/mm/cache-sh5.c')
| -rw-r--r-- | arch/sh/mm/cache-sh5.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/sh/mm/cache-sh5.c b/arch/sh/mm/cache-sh5.c index a50d23c..a8f5142d 100644 --- a/arch/sh/mm/cache-sh5.c +++ b/arch/sh/mm/cache-sh5.c @@ -20,6 +20,8 @@ #include <asm/uaccess.h> #include <asm/mmu_context.h> +extern void __weak sh4__flush_region_init(void); + /* Wired TLB entry for the D-cache */ static unsigned long long dtlb_cache_slot; @@ -27,6 +29,8 @@ void __init cpu_cache_init(void) { /* Reserve a slot for dcache colouring in the DTLB */ dtlb_cache_slot = sh64_get_wired_dtlb_entry(); + + sh4__flush_region_init(); } void __init kmap_coherent_init(void) |