diff options
| author | Paul Mundt <lethal@linux-sh.org> | 2010-04-19 08:27:17 (GMT) |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2010-04-19 08:27:17 (GMT) |
| commit | 3cf6fa1e334a3a4af702f92229690195018b747f (patch) | |
| tree | ebb108e02f13a6e95418245164b45a2a616d421c /arch/sh/mm/cache.c | |
| parent | d9c944463d8f3f7cafaaba8f3e44df62ce817484 (diff) | |
| download | linux-fsl-qoriq-3cf6fa1e334a3a4af702f92229690195018b747f.tar.xz | |
sh: Enable SH-X3 hardware synonym avoidance handling.
This enables support for the hardware synonym avoidance handling on SH-X3
CPUs for the case where dcache aliases are possible. icache handling is
retained, but we flip on broadcasting of the block invalidations due to
the lack of coherency otherwise on SMP.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/mm/cache.c')
| -rw-r--r-- | arch/sh/mm/cache.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/sh/mm/cache.c b/arch/sh/mm/cache.c index 0f4095d..ba401d1 100644 --- a/arch/sh/mm/cache.c +++ b/arch/sh/mm/cache.c @@ -334,6 +334,13 @@ void __init cpu_cache_init(void) extern void __weak sh4_cache_init(void); sh4_cache_init(); + + if ((boot_cpu_data.type == CPU_SH7786) || + (boot_cpu_data.type == CPU_SHX3)) { + extern void __weak shx3_cache_init(void); + + shx3_cache_init(); + } } if (boot_cpu_data.family == CPU_FAMILY_SH5) { |