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authorMatt Fleming <matt@console-pimps.org>2009-12-13 14:38:50 (GMT)
committerPaul Mundt <lethal@linux-sh.org>2009-12-17 05:31:20 (GMT)
commit5d9b4b19f118abfb75e352841f7bf74580d7e427 (patch)
tree5b9d0ec51bd12165d842d1d8a208e7568971757b /arch/sh/mm
parentb73c806341cfc7492ede6a2ce713cb579547d0ab (diff)
downloadlinux-fsl-qoriq-5d9b4b19f118abfb75e352841f7bf74580d7e427.tar.xz
sh: Definitions for 3-level page table layout
If using 64-bit PTEs and 4K pages then each page table has 512 entries (as opposed to 1024 entries with 32-bit PTEs). Unlike MIPS, SH follows the convention that all structures in the page table (pgd_t, pmd_t, pgprot_t, etc) must be the same size. Therefore, 64-bit PTEs require 64-bit PGD entries, etc. Using 2-levels of page tables and 64-bit PTEs it is only possible to map 1GB of virtual address space. In order to map all 4GB of virtual address space we need to adopt a 3-level page table layout. This actually works out better for CONFIG_SUPERH32 because we only waste 2 PGD entries on the P1 and P2 areas (which are untranslated) instead of 256. Signed-off-by: Matt Fleming <matt@console-pimps.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/mm')
-rw-r--r--arch/sh/mm/Kconfig24
-rw-r--r--arch/sh/mm/fault_32.c3
-rw-r--r--arch/sh/mm/init.c6
3 files changed, 30 insertions, 3 deletions
diff --git a/arch/sh/mm/Kconfig b/arch/sh/mm/Kconfig
index 0e7ba8e..b3f6c1a 100644
--- a/arch/sh/mm/Kconfig
+++ b/arch/sh/mm/Kconfig
@@ -190,19 +190,37 @@ config ARCH_MEMORY_PROBE
depends on MEMORY_HOTPLUG
choice
+ prompt "Page table layout"
+ default PGTABLE_LEVELS_3 if X2TLB
+ default PGTABLE_LEVELS_2
+
+config PGTABLE_LEVELS_2
+ bool "2 Levels"
+ help
+ This is the default page table layout for all SuperH CPUs.
+
+config PGTABLE_LEVELS_3
+ bool "3 Levels"
+ depends on X2TLB
+ help
+ This enables a 3 level page table structure.
+
+endchoice
+
+choice
prompt "Kernel page size"
default PAGE_SIZE_8KB if X2TLB
default PAGE_SIZE_4KB
config PAGE_SIZE_4KB
bool "4kB"
- depends on !MMU || !X2TLB
+ depends on !MMU || !X2TLB || PGTABLE_LEVELS_3
help
This is the default page size used by all SuperH CPUs.
config PAGE_SIZE_8KB
bool "8kB"
- depends on !MMU || X2TLB
+ depends on !MMU || X2TLB && !PGTABLE_LEVELS_3
help
This enables 8kB pages as supported by SH-X2 and later MMUs.
@@ -214,7 +232,7 @@ config PAGE_SIZE_16KB
config PAGE_SIZE_64KB
bool "64kB"
- depends on !MMU || CPU_SH4 || CPU_SH5
+ depends on !MMU || CPU_SH4 && !PGTABLE_LEVELS_3 || CPU_SH5
help
This enables support for 64kB pages, possible on all SH-4
CPUs and later.
diff --git a/arch/sh/mm/fault_32.c b/arch/sh/mm/fault_32.c
index 4753010..28e2283 100644
--- a/arch/sh/mm/fault_32.c
+++ b/arch/sh/mm/fault_32.c
@@ -53,6 +53,9 @@ static inline pmd_t *vmalloc_sync_one(pgd_t *pgd, unsigned long address)
if (!pud_present(*pud_k))
return NULL;
+ if (!pud_present(*pud))
+ set_pud(pud, *pud_k);
+
pmd = pmd_offset(pud, address);
pmd_k = pmd_offset(pud_k, address);
if (!pmd_present(*pmd_k))
diff --git a/arch/sh/mm/init.c b/arch/sh/mm/init.c
index 432acd0..761910d 100644
--- a/arch/sh/mm/init.c
+++ b/arch/sh/mm/init.c
@@ -120,7 +120,13 @@ void __init page_table_range_init(unsigned long start, unsigned long end,
for ( ; (i < PTRS_PER_PGD) && (vaddr != end); pgd++, i++) {
pud = (pud_t *)pgd;
for ( ; (j < PTRS_PER_PUD) && (vaddr != end); pud++, j++) {
+#ifdef __PAGETABLE_PMD_FOLDED
pmd = (pmd_t *)pud;
+#else
+ pmd = (pmd_t *)alloc_bootmem_low_pages(PAGE_SIZE);
+ pud_populate(&init_mm, pud, pmd);
+ pmd += k;
+#endif
for (; (k < PTRS_PER_PMD) && (vaddr != end); pmd++, k++) {
if (pmd_none(*pmd)) {
pte = (pte_t *) alloc_bootmem_low_pages(PAGE_SIZE);