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| author | GuanXuetao <gxt@mprc.pku.edu.cn> | 2011-03-04 10:07:48 (GMT) |
|---|---|---|
| committer | GuanXuetao <gxt@mprc.pku.edu.cn> | 2011-03-17 01:19:21 (GMT) |
| commit | 1cf46c42d7688a2e09de87fc9201b0e9a0961866 (patch) | |
| tree | f6bba402319785ed745be62e5b655715626d2761 /arch/unicore32/include/mach/regs-dmac.h | |
| parent | 4fde87cb13a29c06e0b4c2cba86445492098fbc2 (diff) | |
| download | linux-fsl-qoriq-1cf46c42d7688a2e09de87fc9201b0e9a0961866.tar.xz | |
unicore32: modify io_p2v and io_v2p macros, and adjust PKUNITY_mmio_BASEs
1. remove __REG macro
2. add (void __iomem *) to io_p2v macro
3. add (phys_addr_t) to io_v2p macro
4. add PKUNITY_AHB_BASE and PKUNITY_APB_BASE definitions
5. modify all PKUNITY_mmio_BASEs from physical addr to virtual addr
6. adjust prefix macro for all usage of PKUNITY_mmio_BASEs
-- by advice with Arnd Bergmann
Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/unicore32/include/mach/regs-dmac.h')
| -rw-r--r-- | arch/unicore32/include/mach/regs-dmac.h | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/arch/unicore32/include/mach/regs-dmac.h b/arch/unicore32/include/mach/regs-dmac.h index 09fce9d..66de9e7 100644 --- a/arch/unicore32/include/mach/regs-dmac.h +++ b/arch/unicore32/include/mach/regs-dmac.h @@ -5,27 +5,27 @@ /* * Interrupt Status Reg DMAC_ISR. */ -#define DMAC_ISR __REG(PKUNITY_DMAC_BASE + 0x0020) +#define DMAC_ISR (PKUNITY_DMAC_BASE + 0x0020) /* * Interrupt Transfer Complete Status Reg DMAC_ITCSR. */ -#define DMAC_ITCSR __REG(PKUNITY_DMAC_BASE + 0x0050) +#define DMAC_ITCSR (PKUNITY_DMAC_BASE + 0x0050) /* * Interrupt Transfer Complete Clear Reg DMAC_ITCCR. */ -#define DMAC_ITCCR __REG(PKUNITY_DMAC_BASE + 0x0060) +#define DMAC_ITCCR (PKUNITY_DMAC_BASE + 0x0060) /* * Interrupt Error Status Reg DMAC_IESR. */ -#define DMAC_IESR __REG(PKUNITY_DMAC_BASE + 0x0080) +#define DMAC_IESR (PKUNITY_DMAC_BASE + 0x0080) /* * Interrupt Error Clear Reg DMAC_IECR. */ -#define DMAC_IECR __REG(PKUNITY_DMAC_BASE + 0x0090) +#define DMAC_IECR (PKUNITY_DMAC_BASE + 0x0090) /* * Enable Channels Reg DMAC_ENCH. */ -#define DMAC_ENCH __REG(PKUNITY_DMAC_BASE + 0x00B0) +#define DMAC_ENCH (PKUNITY_DMAC_BASE + 0x00B0) /* * DMA control reg. Space [byte] @@ -35,19 +35,19 @@ /* * Source Addr DMAC_SRCADDR(ch). */ -#define DMAC_SRCADDR(ch) __REG(PKUNITY_DMAC_BASE + (ch)*DMASp + 0x00) +#define DMAC_SRCADDR(ch) (PKUNITY_DMAC_BASE + (ch)*DMASp + 0x00) /* * Destination Addr DMAC_DESTADDR(ch). */ -#define DMAC_DESTADDR(ch) __REG(PKUNITY_DMAC_BASE + (ch)*DMASp + 0x04) +#define DMAC_DESTADDR(ch) (PKUNITY_DMAC_BASE + (ch)*DMASp + 0x04) /* * Control Reg DMAC_CONTROL(ch). */ -#define DMAC_CONTROL(ch) __REG(PKUNITY_DMAC_BASE + (ch)*DMASp + 0x0C) +#define DMAC_CONTROL(ch) (PKUNITY_DMAC_BASE + (ch)*DMASp + 0x0C) /* * Configuration Reg DMAC_CONFIG(ch). */ -#define DMAC_CONFIG(ch) __REG(PKUNITY_DMAC_BASE + (ch)*DMASp + 0x10) +#define DMAC_CONFIG(ch) (PKUNITY_DMAC_BASE + (ch)*DMASp + 0x10) #define DMAC_IR_MASK FMASK(6, 0) /* |