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authorRussell King <rmk+kernel@arm.linux.org.uk>2009-09-22 19:54:53 (GMT)
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-09-22 20:01:40 (GMT)
commitae19ffbadc1b2100285a5b5b3d0a4e0a11390904 (patch)
tree3c2086ab67398a019089a47ca3f362a4bc6db74f /arch/x86/include/asm/msr-index.h
parent34e84f39a27d059a3e6ec6e8b94aafa702e6f220 (diff)
parent9173a8ef24a6b1b8031507b35b8ffe5f85a87692 (diff)
downloadlinux-fsl-qoriq-ae19ffbadc1b2100285a5b5b3d0a4e0a11390904.tar.xz
Merge branch 'master' into for-linus
Diffstat (limited to 'arch/x86/include/asm/msr-index.h')
-rw-r--r--arch/x86/include/asm/msr-index.h11
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index bd55490..4ffe09b 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -81,8 +81,15 @@
#define MSR_IA32_MC0_ADDR 0x00000402
#define MSR_IA32_MC0_MISC 0x00000403
+#define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x))
+#define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x))
+#define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x))
+#define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x))
+
/* These are consecutive and not in the normal 4er MCE bank block */
#define MSR_IA32_MC0_CTL2 0x00000280
+#define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x))
+
#define CMCI_EN (1ULL << 30)
#define CMCI_THRESHOLD_MASK 0xffffULL
@@ -215,6 +222,10 @@
#define THERM_STATUS_PROCHOT (1 << 0)
+#define MSR_THERM2_CTL 0x0000019d
+
+#define MSR_THERM2_CTL_TM_SELECT (1ULL << 16)
+
#define MSR_IA32_MISC_ENABLE 0x000001a0
/* MISC_ENABLE bits: architectural */