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| author | Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> | 2009-04-07 01:51:29 (GMT) |
|---|---|---|
| committer | Len Brown <len.brown@intel.com> | 2009-04-07 22:17:51 (GMT) |
| commit | db954b5898dd3ef3ef93f4144158ea8f97deb058 (patch) | |
| tree | 781b62baa5aa262fca99198ba326e5e9cc44b26a /arch/x86/include/asm | |
| parent | 577c9c456f0e1371cbade38eaf91ae8e8a308555 (diff) | |
| download | linux-fsl-qoriq-db954b5898dd3ef3ef93f4144158ea8f97deb058.tar.xz | |
x86 ACPI: Add support for Always Running APIC timer
Add support for Always Running APIC timer, CPUID_0x6_EAX_Bit2.
This bit means the APIC timer continues to run even when CPU is
in deep C-states.
The advantage is that we can use LAPIC timer on these CPUs
always, and there is no need for "slow to read and program"
external timers (HPET/PIT) and the timer broadcast logic
and related code in C-state entry and exit.
Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Acked-by: H. Peter Anvin <hpa@zytor.com>
Signed-off-by: Len Brown <len.brown@intel.com>
Diffstat (limited to 'arch/x86/include/asm')
| -rw-r--r-- | arch/x86/include/asm/cpufeature.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index 0beba0d..bb83b1c 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -154,6 +154,7 @@ * CPUID levels like 0x6, 0xA etc */ #define X86_FEATURE_IDA (7*32+ 0) /* Intel Dynamic Acceleration */ +#define X86_FEATURE_ARAT (7*32+ 1) /* Always Running APIC Timer */ /* Virtualization flags: Linux defined */ #define X86_FEATURE_TPR_SHADOW (8*32+ 0) /* Intel TPR Shadow */ |