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author | Takashi Iwai <tiwai@suse.de> | 2012-09-05 07:17:31 (GMT) |
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committer | Takashi Iwai <tiwai@suse.de> | 2012-09-05 07:17:31 (GMT) |
commit | 14e42917216ab0859827c2d8024df45a917301b4 (patch) | |
tree | efbea5d1c54387d62a6fd66a21560232cf312fda /arch/x86/kernel/cpu/perf_event.h | |
parent | 292f2b6254c9dbb98def6d3521b07a837545ead0 (diff) | |
parent | 4266274836e81575ee82498d84f4bd08ab7a7378 (diff) | |
download | linux-fsl-qoriq-14e42917216ab0859827c2d8024df45a917301b4.tar.xz |
Merge branch 'fixes' of git://git.alsa-project.org/alsa-kernel into for-next
Diffstat (limited to 'arch/x86/kernel/cpu/perf_event.h')
-rw-r--r-- | arch/x86/kernel/cpu/perf_event.h | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/x86/kernel/cpu/perf_event.h b/arch/x86/kernel/cpu/perf_event.h index 821d53b..6605a81 100644 --- a/arch/x86/kernel/cpu/perf_event.h +++ b/arch/x86/kernel/cpu/perf_event.h @@ -516,6 +516,26 @@ static inline bool kernel_ip(unsigned long ip) #endif } +/* + * Not all PMUs provide the right context information to place the reported IP + * into full context. Specifically segment registers are typically not + * supplied. + * + * Assuming the address is a linear address (it is for IBS), we fake the CS and + * vm86 mode using the known zero-based code segment and 'fix up' the registers + * to reflect this. + * + * Intel PEBS/LBR appear to typically provide the effective address, nothing + * much we can do about that but pray and treat it like a linear address. + */ +static inline void set_linear_ip(struct pt_regs *regs, unsigned long ip) +{ + regs->cs = kernel_ip(ip) ? __KERNEL_CS : __USER_CS; + if (regs->flags & X86_VM_MASK) + regs->flags ^= (PERF_EFLAGS_VM | X86_VM_MASK); + regs->ip = ip; +} + #ifdef CONFIG_CPU_SUP_AMD int amd_pmu_init(void); |