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| author | Stephane Eranian <eranian@google.com> | 2013-01-24 15:10:33 (GMT) |
|---|---|---|
| committer | Arnaldo Carvalho de Melo <acme@redhat.com> | 2013-04-01 15:16:49 (GMT) |
| commit | a63fcab45273174e665e6a8c9fa1a79a9046d0d5 (patch) | |
| tree | 9e226f2d0b16af00e07762cef783c7cae2b27b15 /arch/x86/kernel | |
| parent | f20093eef5f7843a25adfc0512617d4b1ff1aa6e (diff) | |
| download | linux-fsl-qoriq-a63fcab45273174e665e6a8c9fa1a79a9046d0d5.tar.xz | |
perf/x86: Export PEBS load latency threshold register to sysfs
Make the PEBS Load Latency threshold register layout
and encoding visible to user level tools.
Signed-off-by: Stephane Eranian <eranian@google.com>
Cc: peterz@infradead.org
Cc: ak@linux.intel.com
Cc: acme@redhat.com
Cc: jolsa@redhat.com
Cc: namhyung.kim@lge.com
Link: http://lkml.kernel.org/r/1359040242-8269-10-git-send-email-eranian@google.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Diffstat (limited to 'arch/x86/kernel')
| -rw-r--r-- | arch/x86/kernel/cpu/perf_event_intel.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c index d5ea5a0..ae6096b 100644 --- a/arch/x86/kernel/cpu/perf_event_intel.c +++ b/arch/x86/kernel/cpu/perf_event_intel.c @@ -1781,6 +1781,8 @@ static void intel_pmu_flush_branch_stack(void) PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63"); +PMU_FORMAT_ATTR(ldlat, "config1:0-15"); + static struct attribute *intel_arch3_formats_attr[] = { &format_attr_event.attr, &format_attr_umask.attr, @@ -1791,6 +1793,7 @@ static struct attribute *intel_arch3_formats_attr[] = { &format_attr_cmask.attr, &format_attr_offcore_rsp.attr, /* XXX do NHM/WSM + SNB breakout */ + &format_attr_ldlat.attr, /* PEBS load latency */ NULL, }; |