powerpc: Enable erratum A-008007 workaorund for T1040 Rev1.0

Erratum A-008007 states that PVR register value is unreliable for
e5500 cores (Major revision 1.0, Minor revision 2.0) which are
present in T1040 Rev1.0 SoC.

This workaround implementation
-adds a new config option 'CONFIG_FSL_ERRATUM_A_008007' in t1040
 specific defconfig files. This config option is used to make
 sure that changes does not impact non-T1040 platforms.
-replaces mfspr(x) macro defintion to check if above erratum is
 defined and if x is same as SPRN_PVR, then return static value
 else call mfspr instruction.
-Similarly replaces mfpvr() calls

TODO:
1.Use some cleaner approach like reading SVR rgeister or parse
 device tree to check if T1040 Rev1.0 Si instead of using config option.

2.This patch only replaces current accesses of PVR register but
 does not restrict any new code which tries to read this.
 A mechanism needs to be implemented to restrict this.

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Change-Id: Ib5f17dec01ca0d98c5f506b1be23dfe06a541015
Reviewed-on: http://git.am.freescale.net:8181/12350
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>

8 files changed, 36 insertions, 0 deletions

diff --git a/arch/powerpc/boot/util.S b/arch/powerpc/boot/util.S
index 6636b1d..b42619e 100644
--- a/arch/powerpc/boot/util.S
+++ b/arch/powerpc/boot/util.S
@@ -42,6 +42,7 @@ timebase_period_ns:
  */
 	.globl	udelay
 udelay:
+#ifndef CONFIG_FSL_ERRATUM_A_008007 /*PVR value for e5501 is unreliable*/
 	mfspr	r4,SPRN_PVR
 	srwi	r4,r4,16
 	cmpwi	0,r4,1		/* 601 ? */
@@ -53,6 +54,7 @@ udelay:
 	subic.	r3,r3,1
 	bne	00b
 	blr
+#endif
 
 .udelay_not_601:
 	mulli	r4,r3,1000	/* nanoseconds */
diff --git a/arch/powerpc/configs/t1040_32bit_smp_defconfig b/arch/powerpc/configs/t1040_32bit_smp_defconfig
index f7c321b..a401e7c 100644
--- a/arch/powerpc/configs/t1040_32bit_smp_defconfig
+++ b/arch/powerpc/configs/t1040_32bit_smp_defconfig
@@ -20,6 +20,7 @@ CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
 CONFIG_MODVERSIONS=y
+CONFIG_FSL_ERRATUM_A_008007=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_MAC_PARTITION=y
diff --git a/arch/powerpc/configs/t1040_64bit_smp_defconfig b/arch/powerpc/configs/t1040_64bit_smp_defconfig
index 86bd8f7..1b987d9 100644
--- a/arch/powerpc/configs/t1040_64bit_smp_defconfig
+++ b/arch/powerpc/configs/t1040_64bit_smp_defconfig
@@ -22,6 +22,7 @@ CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
 CONFIG_MODVERSIONS=y
+CONFIG_FSL_ERRATUM_A_008007=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_MAC_PARTITION=y
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 5402fb1..977cba5 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -1070,6 +1070,8 @@
 #define PVR_VER_E500V1	0x8020
 #define PVR_VER_E500V2	0x8021
 #define PVR_VER_E6500	0x8040
+#define PVR_VER_E5500	0x8024
+#define PVR_VER_E5500_REV_1020	0x1020
 
 /*
  * For the 8xx processors, all of them report the same PVR family for
@@ -1127,9 +1129,21 @@
 				     : "memory")
 #endif
 
+#ifdef CONFIG_FSL_ERRATUM_A_008007 /*PVR value for e5501 is unreliable*/
+#define mfspr(rn)	({unsigned long rval; \
+			  if (rn == SPRN_PVR) {\
+				rval = (PVR_VER_E5500 << 16) | \
+					PVR_VER_E5500_REV_1020; \
+			  } else {\
+				asm volatile("mfspr %0," __stringify(rn) \
+					: "=r" (rval)); \
+			  } \
+			  rval; })
+#else
 #define mfspr(rn)	({unsigned long rval; \
 			asm volatile("mfspr %0," __stringify(rn) \
 				: "=r" (rval)); rval;})
+#endif
 #define mtspr(rn, v)	asm volatile("mtspr " __stringify(rn) ",%0" : \
 				     : "r" ((unsigned long)(v)) \
 				     : "memory")
diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
index 911f3b4..5d30068 100644
--- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
+++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
@@ -57,6 +57,7 @@ _GLOBAL(has_pw20_altivec_idle)
 	/* 0 false, 1 true */
 	li	r3, 0
 
+#ifndef CONFIG_FSL_ERRATUM_A_008007 /*PVR value for e5501 is unreliable*/
 	/* PW20 & AltiVec idle feature only exists for E6500 */
 	mfspr	r0, SPRN_PVR
 	rlwinm	r11, r0, 16, 16, 31
@@ -70,6 +71,7 @@ _GLOBAL(has_pw20_altivec_idle)
 	cmpwi	r11, 0x20
 	blt	2f
 	li	r3, 1
+#endif
 2:
 	blr
 
diff --git a/arch/powerpc/kernel/fsl_booke_cache.S b/arch/powerpc/kernel/fsl_booke_cache.S
index 767c237..c0a3efd 100644
--- a/arch/powerpc/kernel/fsl_booke_cache.S
+++ b/arch/powerpc/kernel/fsl_booke_cache.S
@@ -75,7 +75,9 @@ _GLOBAL(__flush_disable_L1)
 	lis	r5, 0
 	ori	r5, r5, PVR_E6500@l
 	cmpw	r4, r5
+#ifndef CONFIG_FSL_ERRATUM_A_008007 /*PVR value for e5501 is unreliable*/
 	beq	2f
+#endif
 	mflr	r10
 	bl	flush_dcache_L1	/* Flush L1 d-cache */
 	mtlr	r10
diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S
index dc0488b..3eb57ff 100644
--- a/arch/powerpc/kernel/head_32.S
+++ b/arch/powerpc/kernel/head_32.S
@@ -1059,6 +1059,7 @@ _ENTRY(switch_mmu_context)
  */
 clear_bats:
 	li	r10,0
+#ifndef CONFIG_FSL_ERRATUM_A_008007 /*PVR value for e5501 is unreliable*/
 	mfspr	r9,SPRN_PVR
 	rlwinm	r9,r9,16,16,31		/* r9 = 1 for 601, 4 for 604 */
 	cmpwi	r9, 1
@@ -1081,6 +1082,7 @@ clear_bats:
 	mtspr	SPRN_IBAT2L,r10
 	mtspr	SPRN_IBAT3U,r10
 	mtspr	SPRN_IBAT3L,r10
+#endif
 BEGIN_MMU_FTR_SECTION
 	/* Here's a tweak: at this point, CPU setup have
 	 * not been called yet, so HIGH_BAT_EN may not be
@@ -1132,6 +1134,7 @@ mmu_off:
  */
 initial_bats:
 	lis	r11,PAGE_OFFSET@h
+#ifndef CONFIG_FSL_ERRATUM_A_008007 /*PVR value for e5501 is unreliable*/
 	mfspr	r9,SPRN_PVR
 	rlwinm	r9,r9,16,16,31		/* r9 = 1 for 601, 4 for 604 */
 	cmpwi	0,r9,1
@@ -1150,6 +1153,7 @@ initial_bats:
 	mtspr	SPRN_IBAT2L,r8
 	isync
 	blr
+#endif
 
 4:	tophys(r8,r11)
 #ifdef CONFIG_SMP
diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype
index 1211e3b..c9ef8a5 100644
--- a/arch/powerpc/platforms/Kconfig.cputype
+++ b/arch/powerpc/platforms/Kconfig.cputype
@@ -232,6 +232,16 @@ config FSL_ERRATUM_A_006184_PERIOD
 	  since when idle we will always have just executed from the main
 	  kernel mapping, so it should not be absent from the L1 I-MMU.
 
+config FSL_ERRATUM_A_008007
+	bool "Work around erratum A-008007 (pvr value)"
+	default n
+	help
+	  This works around erratum A-008007 by not using PVR value read from
+	  PVR register as it is unreliable for e5500 core
+	  (major version:1.0, minor version: 2.0 ).
+	  Instead use expected hard-code value for PVR register for core.
+	  Say Y if and only if you using T1040 Rev1.0 Silicon
+
 config PPC_DISABLE_THREADS
 	bool "Avoid the use of hardware threads"
 	help